Hi,

I am trying to simulate the effect of clock jitter on the performance of an N-path filter. To this end, I need to generate four 25% non-overlapping clocks. It seems that I have successfully generated these clocks; however, when using these clocks, the pss simulation does not converge!

I would really appreciate any comment!

To model the jitter, I am using the following Verilog-a code:

**Code:**// VerilogA for 4thOrder, JitteryClk4, veriloga
`include "constants.vams"
`include "disciplines.vams"
module JitteryClk4(clkin, clkoutp, clkoutn, vdd, vss);
input clkin;
output clkoutp, clkoutn;
inout vdd, vss;
electrical clkin, clkoutp, clkoutn, vdd, vss;
parameter jitter=1p;
real statep, staten, threshold;
analog begin
threshold = 0.5 + ($random() % 100) * jitter/(100*50p);
@(cross(V(clkin) - threshold))
begin
end
statep = V(clkin) > threshold;
staten = V(clkin) < threshold;
V(clkoutp) <+ transition(statep, 0, 50p, 50p);
V(clkoutn) <+ transition(staten, 0, 50p, 50p);
end
endmodule

The clkin input of the above code, which will be applied in the top-level schematic of my circuit, is a 1-GHz, 50% signal which has rise- and falltime of 50ps. (In the above code, I suppose that the jitter is 1ps and then, considering the 50-ps rise- and falltime, I calculate a threshold voltage based on the jitter and slope of the rising or falling clock. Finally, I use this threshold voltage to randomly vary the edges of the ideal input clock clkin. I hope this method is okay!).

The output of this code is a 50% 1-GHz clock where the edges experience a random jitter.

Now, I only need to generate four ideal 500MHz, 25%, non-overlapping clocks in my schematic and AND these ideal clocks with either clkoutp or clkoutn. In this way, the edges of the 25% clocks experience the jitter produced by the above code. To further clarify, I name the ideal 500MHz, 25% non-overlapping clocks Phi0, Phi1, Phi2, and Phi3. Phi0, the first 25% clock, can be ANDed with clkoutp. Phi1, the second 25% clokc, can be ANDed with clkoutn, and ...

One last point, if we assume jitter=0, the Verilog-a code will produce a delay of 25ps between the output clock (clkoutp, clkoutn) and the input clock (clkin). So I am applying an extra 25ps delay to the ideal 25% clocks. In other words, Phi0, Phi1, Phi2, and Phi3 have a delay of 25ps, 525ps, 1025ps, and 1525ps, respectively.

By the way, the AND function is achieved through the vcvsp blocks.