Gp
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Hi,
I have design and testbench both are in Verilog-ams As shown in below. And tried with -assert option. it is working fine now.
Now I want to try the following example with design in Verilog-AMS and test bench in System Verilog. So, is it Possible? How? And How to bind this example with VUNIT?
//************************ Design (test.vams) *************************// `timescale 1ns/1ps `include "disciplines.vams"
module test (in,out); inout in,out; electrical in,out;
analog begin V(out) <+ 3.0 + V(in); end //psl out_check: assert always ({V(out)> 5.0}) @(cross (V(in)-0.5));
endmodule *********************************************************
//********************** Testbench (test_tb.vams) *****************
module test_tb (in_tb,out_tb); inout in_tb,out_tb; electrical in_tb,out_tb;
// analog begin // V(in_tb)<+ 1.0; // end vsource #(.type("pwl"), .wave({"0","0","5n","0","6n","1","9n","1","10n","0"})) V0 ( in_tb , cds_globals.\gnd! );
test dut (.in (in_tb), .out (out_tb));
endmodule
//**********************************************************************
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