Gp
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Hi, I want to use following Verilog-ams macro for range check in cadence environment: `RANGE_CHECK(expr,"NAME", max,min,ef,en)For detailed reference, use following link: https://books.google.co.in/books?id=RKrfAwAAQBAJ&pg=PA92&lpg=PA92&dq=%60AVDD+che... ck+in+mixed+signal+methodology+guide&source=bl&ots=uXomWUVSRy&sig=s37V_5RGMGbK0q wNuanhB1qqpJo&hl=en&sa=X&ved=0ahUKEwjq2PH27_7VAhWKhVQKHUS5CXkQ6AEINjAD#v=onepage &q=%60AVDD%20check%20in%20mixed%20signal%20methodology%20guide&f=false
So, How to use this type of macro in Verilog-ams? When I use, error through about "this type of macro doesn't support".
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