polyam
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Hi,
I am using the following Verilog AMS code as a Phase Frequency Detector(PFD) and the symbol has been correctly created. -------------------------------------------------------------------------------- ------ //Verilog-AMS HDL
`include "constants.vams" `include "disciplines.vams" `timescale 10ps/1ps module PFD (up,dn,fref,fdiv);
input fref; input fdiv; output up,dn;
wire fv_rst , fr_rst; wire reset; reg q0,q1;
assign fr_rst=reset | (q0&q1); assign fv_rst=reset | (q0&q1); assign reset=fref & fdiv;
always @ (posedge fdiv or posedge fv_rst) begin if (fv_rst) q0<=0 ; else q0<=1; end
always @ (posedge fref or posedge fr_rst) begin if (fr_rst) q1<=0 ; else q1<=1; end
assign up=q1; assign dn=q0;
endmodule --------------------------------------------------------------- I also created a test bench along with a Config view (Use Template --> Name: AMS). In the ADE L, I switched to ams as a simulator. Running the simulation gives me the following error:
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Successfully compiled ('PLL' 'PFD_TB' 'schematic'). Compilation successful.
ncelab: *W,AMSNEWSFE: You have set the environment variable AMS_NEW_SFE. This is no longer needed as IUS 9.2 and above only works in new SFE mode. Elaborating the design hierarchy: ncelab: *N,SFEDPL: Deploying new SFE in analog engine. Discipline resolution Pass... net5 ), .dn( DN ), .up( UP ), .fref( net6 ) ); | ncelab: *E,CUVNCM (./ihnl/PLL/PFD_TB/schematic/verilog.vams,20|3): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance PFD_TB.I7. net5 ), .dn( DN ), .up( UP ), .fref( net6 ) ); | ncelab: *E,CUVNCM (./ihnl/PLL/PFD_TB/schematic/verilog.vams,20|40): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance PFD_TB.I7.
Failed to elaborate ("PLL" "PFD_TB" "config"). ---------------------------------------------------------------
I do appreciate any help :).
Tnx
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