I want to simulate the extracted spice netlist with schematics, behavioral models uing Virtuoso AMS simulator and ADEXL.

Simulator should pick up the desired spice netlist based on the lib variable which has given during simulation.

spice netlist is like this

.LIB ext1
.include ./entrcp1
....
.LIB ext8
.include ./entrcp8s
....

I tried to set up a global variable and corner variable like
pick_netlist = ext1 in ADEXL

But AMS simulator interprets as real number variable and gives me the error. I was able to run the simulation with pick_netlist = "ext1", but it does not include the desired extracted netlist.

The flow I was looking for is working fine with spectre simulator but not with AMS.

Is there any alternative solution that I can use to include the spice netlist in verilog-ams netlist created by AMS?

Thanks in advance