davidshw
Junior Member

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Posts: 12
China
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if a verilog-a module has an array parameter, such as
moduel test (A,B) parameter integer p1[1:4]='{1,2,3,4} ; analog begin ... ... end endmoudle
when instantiating this module in hspice or spectre, how to override the array parameter? xdut a b test p1=???
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