Jacki
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Hi,
Recently I start to consider the gidl leakage current and popcorn noise when I use the bulk CMOS technology below 65nm. It looks I cannot do anything to reduce the gidl leakage, but be careful about the Vgs voltage. Does anybody know how to reduce the gidl leakage in the circuit design. About the popcorn noise, normally I don't pay attention to this noise. But it has the similar characteristics as the 1/f noise. Can anybody comment on it, how to reduce it? Thank you.
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