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Oct 20th, 2019, 1:46am
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How to jump from a forever cycling loop in Veriloga. (Read 1102 times)
Jacki
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How to jump from a forever cycling loop in Veriloga.
Feb 06th, 2018, 7:19am
 
Hello,

   I am writing a Veriloga model to do a binary search. The basic idea is: I have an open loop oscillator with binary control signals. I want to control the oscillating frequency to a range. The easiest way is to start the search from 00000 (5-bit) and linearly increase to 11111. But it takes too much simulation time (it is oscillator in time domain simulation).
   So I plan to do a binary search, and now I have a forever loop : for example
   while(1) begin
   ...
   break;
    end
   What I want is how to quit the forever loop if the frequency meets my range? In Verilog code, it is just a command "break", but I don't know how to do it in Veriloga.
   Any help is highly appreciated.
   By the way, several functions in Verilog don't work in Veriloga, for example
   @(posedge clk_in)
   break;
   #1u;

   If you have some good examples about the timing circuits, that would be wonderful.
   Thank you.
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Geoffrey_Coram
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Re: How to jump from a forever cycling loop in Veriloga.
Reply #1 - Feb 6th, 2018, 8:57am
 
Why not have a variable "found" that you initialize to 0, set to 1 when your search is done, and use that in the while condition?

 while (!found) begin
...
 end
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If at first you do succeed, STOP, raise your standards, and stop wasting your time.
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