yong_rfic
Junior Member
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Posts: 13
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Hello,
I have encountered netlist errors when trying to simulate circuit which has two simple Verilog-A blocks. Each individual block can be nestlisted successfully. However when I put them in the same schematic, there are errors. The error messages are:
"ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I1' in design 'RF14/cal_logic_decod/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n" and many more of the same thing...
The two verilog-a blocks are defined like
module A(B_in, T_out);
input [4:0] B_in ; electrical [4:0] B_in ; output [15:0] T_out ; electrical [15:0] T_out ;
endmodule
module B(clk, vin, vout);
input vin, clk; output [4:0] vout; electrical vin, clk; electrical [4:0] vout;
endmodule
Please advise, thank you.
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