Jacki
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Hello,
I am writing a Veriloga model to do a binary search. The basic idea is: I have an open loop oscillator with binary control signals. I want to control the oscillating frequency to a range. The easiest way is to start the search from 00000 (5-bit) and linearly increase to 11111. But it takes too much simulation time (it is oscillator in time domain simulation). So I plan to do a binary search, and now I have a forever loop : for example while(1) begin ... break; end What I want is how to quit the forever loop if the frequency meets my range? In Verilog code, it is just a command "break", but I don't know how to do it in Veriloga. Any help is highly appreciated. By the way, several functions in Verilog don't work in Veriloga, for example @(posedge clk_in) break; #1u;
If you have some good examples about the timing circuits, that would be wonderful. Thank you.
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