Hi all,

maybe this is a noob question... I'm verifying the discrete-time Voltage Controlled Oscillator (VCO) of Simulink's Communication System Toolbox; the final target is a bang-bang PLL high-level analysis. The VCO has a gain of 1MHz/V and a central frequency of 10MHz. I've put a sinusoidal signal (1kHz) to his input and a comparator to his output because I'm interested in a square-wave signal. The simulation model is depicted in the attachment.

My doubt regards the parameters for a correct simulation of the VCO. I'm using a fixed-step solver with a step size of 100us, i.e. a simulation frequency of 10 times the maximum frequency of the VCO. With a script, I'm calculating the output frequency of the VCO (see attachment) and as you can see this is far away from a sinusoid!

Now the question: how to chose correctly the step size of the simulation for the VCO verification?

Best regards.