dog1
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Thanks V Roy, that's very helpful. so can I conclude that due to power consideration, it doesn't make too much sense to have the P and S counter in the pulse swallow counter syncronized? And that the only syncronized part may be the pre-scaler?
Also, I would like to understand better the advantage of swallow counter in high speed case. If I have a synced div4 counter followed by a ripple counter, would it be comparible in performance (power, speed) but less in complexity than a swallow counter? Or would swallow counter be higher speed? I attached a drawing to show my idea. For example, In swallow counter case, the pre-scaler count 3 or 4.
From power perspective, they are similar. Becasue they both have around 2 bits async and the rest sync.
From speed perspective, for swallow counter, the latest time for the state to change from count 3-> count 4 or the other way round is t1=N x T, where N is a integral (in this case, 1 or 2) and T is the input clock period. Then t1 must be smaller than delay1 and delay2. Whereas in the ripple counter case, T must be smaller than delay3. I think this can be an advantage for swallow counter, because t1 can be larger than T, and the delay1/2 can be similar than delay3. But I am not sure if this is the only reason that swallow counter is prefered in high speed design (eg. PLL design) over the binary structure.
Thanks. Chen
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