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Oct 20th, 2019, 1:20am
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LDMOS in DNW (Read 1001 times)
neoflash
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LDMOS in DNW
Jun 08th, 2018, 12:05pm
 
Can TSMC LDMOS bulk be a separate P-well and tied to its own source, to reduce body effect? Like a traditional MOSFET?

Thanks.
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Geoffrey_Coram
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Re: LDMOS in DNW
Reply #1 - Jun 15th, 2018, 8:43am
 
That's probably proprietary information that the foundry won't want on a public web site. You should probably contact the foundry (or read the documentation for whatever process it is that you're using).
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Horror Vacui
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Re: LDMOS in DNW
Reply #2 - Jun 17th, 2018, 12:40pm
 
I see no theoretical obstacles, that's why you have DNW in the technology. What is the source of your doubt? If you run a simulation with the most equipped model and spectre throws an assert/warning about it, than it has a reason. People has taken extra efforts to add these checks into the model file. Especially if the model maturity is high.
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