The Designer's Guide Community
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Sep 27th, 2021, 5:50pm
Pages: 1
Send Topic Print
simulating .va files in hspice (Read 693 times)
New Member

Posts: 2

simulating .va files in hspice
Mar 17th, 2019, 11:43am

I'm working on simulating an ideal delta sigma modulator in hspice and I need to use ideal models for different parts of my circuit. for example I want to simulate the model in hspice for a 3rd level quantizer. I follow the manual for simulating this kind of models in hspice but unfortunately it is not working. I will appreciate if anyone can help me.
the .va and .sp files are attached below and are written too.
Also the problem is that when I simulate the test.sp in hspice nothing happen and the .lis file is empty and no error and other information is shown.
. file:

// N-level triggered quantizer (like an ADC followed by a DAC)
// Version 1b, 17 July 03
// Ken Kundert
// Downloaded from The Designer's Guide (
// Post any questions to

`include "disciplines.vams"

module quantizer (out, in, clk);

output out; voltage out;// output
input in; voltage in;      // input
input clk; voltage clk;      // clock input (edge triggered)
parameter integer levels=2 from [2:inf);// number of quantization levels
parameter real vh = +1;                  // voltage of highest level
parameter real vl = -1 from (-inf:vh);      // voltage of lowest level
parameter real vth = (vh + vl)/2;      // threshold voltage of clock
parameter integer dir = +1 from [-1:+1] exclude 0;
                 // if dir=+1, rising clock edge triggers
                 // if dir=-1, falling clock edge triggers
parameter real td = 0 from [0:inf);      // output delay
parameter real tt = 0 from [0:inf);      // output transition time
real quantized, delta;
integer level;

analog begin
   @(cross(V(clk) - vth, dir) or initial_step) begin
     delta = (vh-vl)/(levels-1);
     level = (V(in)-vl)/delta;
     if (level < 0)
         level = 0;
     else if (level >= levels)
         level = levels-1;
     quantized = level * delta + vl;
   V(out) <+ transition( quantized, td, tt );

test.sp file:

Title: testing verilog-A
.options post=1

VCLK      clk      0            pulse      0 1 1f 1f 1f 0.390625u 0.78125u
Vin      in            0            SIN      0 1 2k

Xquantizer1            out            in            clk      quantizer      levels=3 vh=1 vl=-1 vth =0 dir=1 td=0 tt=0
RL      out            0            1meg

.option method=gear post=1
.options delmax=10n
.temp 25
.tran 10n 20m


Back to top
« Last Edit: Mar 17th, 2019, 3:29pm by masoumeh »  
View Profile   IP Logged
Ken Kundert
Global Moderator

Posts: 2312
Silicon Valley
Re: simulating .va files in hspice
Reply #1 - Mar 17th, 2019, 3:12pm
If you want help, it is probably best to simply show the .va and .sp files rather than force people to download and unpack them. Also, you should give the error message or at least describe what is going wrong.

The way it currently stands, you are expecting people to do a bunch of work before they have any indication as to whether they can help you or not.

Back to top
View Profile WWW   IP Logged
New Member

Posts: 2

Re: simulating .va files in hspice
Reply #2 - Mar 17th, 2019, 3:31pm
Thank you for your comment, I edited the post.
Back to top
View Profile   IP Logged
Andrew Beckett
Senior Fellow

Life, don't talk to
me about Life...

Posts: 1737
Bracknell, UK
Re: simulating .va files in hspice
Reply #3 - Mar 18th, 2019, 7:18am
The main issue is that you have vth=0 on the instance line for the quantizer, and since the clock transitions between 0 and 1V, it never crosses the threshold. Set it to 0.5 instead.

You also have your rise, fall and delay for the clock source set to the ridiculously short 1fs. That is going to make the simulator slower by trying to follow these unrealistically short transition times. Similarly you should set tt on the quantizer instance to be greater than 0. So I would suggest:

VCLK	clk	0		pulse	0 1 100p 100p 100p 0.390625u 0.78125u

Xquantizer1		out		in		clk	quantizer	levels=3 vh=1 vl=-1 vth =0.5 dir=1 td=0 tt=100p 

I ran this in spectre (with the same netlist) and it then works fine. Even 100ps rise time/transition may be shorter than you really need if you've got a 1.28MHz clock. That said, for spectre it didn't affect the speed that much between 100p or 1n.

Back to top
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2021 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to Consider submitting a paper or model.