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May 25th, 2020, 4:14pm
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Settling of switched capacitor Circuit in hold mode (Read 78 times)
Mohamed Osama
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Settling of switched capacitor Circuit in hold mode
Mar 23rd, 2019, 7:12am
Hello everyone
I want to ask about something in the unity gain sampler
the images are from Razavi's book "Design of Analog CMOS"

He says through the chapter 13  of switched capacitor circuit that node x is floating and hence its charge must be conserved, however when he explained the settling in the hold me he allowed the voltage of node x to change very abruptly so that the KVL holds, however does not that violate the conservation of charge at that node? Notice that : Vout starts at 0 voltage, and the voltage across CH is Vo due to sampling phase also Vx was 0 voltage before that jump.
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Re: Settling of switched capacitor Circuit in hold mode
Reply #1 - May 7th, 2019, 5:42am
To understand this I will suggest you to have the look on the lecture notes/Vedios of Vishal SAXENA,where is explained in a lucid way
here is the link

Also there is another Prof. Dr. Shanti Pavan. There are free youtube vedios of him on switch capacitor circuits, which would be very useful to buildup the fundamental concepts.

Good LUCK!
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Always a learner and will be .
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