The most efficient way to reduce charge conservation errors is to tighten reltol while loosing lteratio at the same time (reltol is a simulator option while lteratio is a transient option).  Tightening reltol tightens the control of both KCL errors and timesteps. But shrinking the timestep does not help with conservation errors, so you can reduce the slowdown you experience by loosening lteratio, which only affects the time steps.  If you tighten reltol and loosen lteratio by the same amount then you should get roughly the same number of time points while controlling conservation errors.

Having said that, if you are having conservation errors, you should check your capacitor models. Many nonlinear capacitor models written in Verilog-A have charge conservation problems. If you are using such model you are doomed.

-Ken