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oscilalting convergence residue w/ veriloga signal generator (Read 31 times)
Horror Vacui
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oscilalting convergence residue w/ veriloga signal generator
Jul 24th, 2019, 5:28am
 
Hello Everybody,

I am looking for hints to solve a convergence issue, what I face when I run a post-layout spectre simulation with a veriloga block.

Spectre oscillates between solutions at many points, and after a while it throws an error:
Code:
iter = 56, convergence failed at solution: SIM_CONTROL:Out_vss_flow (Soln = -5.97066 mA Delta = -3.04431 A), residue: SIM_CONTROL:Out_vss_flow (RESIDUE= -43.7835 mV REF = 692.316 mV)
iter = 57, convergence failed at solution: SIM_CONTROL:Out_vss_flow (Soln = 3.03834 A Delta = 3.04431 A), residue: SIM_CONTROL:Out_vss_flow (RESIDUE= 43.7835 mV REF = 692.316 mV)
iter = 58, convergence failed at solution: SIM_CONTROL:Out_vss_flow (Soln = -5.97066 mA Delta = -3.04431 A), residue: SIM_CONTROL:Out_vss_flow (RESIDUE= -43.7835 mV REF = 692.316 mV)
iter = 59, convergence failed at solution: SIM_CONTROL:Out_vss_flow (Soln = 3.03834 A Delta = 3.04431 A), residue: SIM_CONTROL:Out_vss_flow (RESIDUE= 43.7835 mV REF = 692.316 mV) 



So it points me towards bad modelling like the case of abs(sqrt(x)) function.  In a pre-layout (=schematic) simulation everything is fine, but using an RCC or CC extraction I got these errors.

SIM_CONTROL is the name of the veriloga instance, what I use to adaptively control the simulation. Its output signal is Out and vss is the ground. The error is that the current going out this terminal can not be determined with Nweton-raphson. The code for setting the output is:
Code:
phase = `M_TWO_PI*idtmod(fc,0,1,0);
V(Out,vss) <+ out_DC + vout*cos(phase);
 


The value "vout" and fc is swept adaptively in the code. I've used the transition() filter on vout, but it did not help changed the convergence.

Is there anything wrong with this verilogA code snippet? Could it cause the linked error? I am no verilogA expert, but either this, or the parasitic extraction add something to the circuit what drives the simulator in that state or  something in the PDK models is the culprit. How could I reduce the scope and find a correct diagnoses?

PS: I've tried different PDK/model versions as well as different MMSIM versions. The latest was MMSIM18.10.077.


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« Last Edit: Jul 24th, 2019, 7:03am by Horror Vacui »  
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Horror Vacui
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Re: oscilalting convergence residue w/ veriloga signal generator
Reply #1 - Jul 24th, 2019, 7:01am
 
A side question related to the debug message. How is the debug message to be interpreted. Am I right if I state the following based on the error message:
- the current from the output terminal was -5.97mA in the current iteration step, which is 3.04A smaller than in the previous iteration step

On the other hand I am in the dark regarding how to interpret correctly the voltage part. REF=692.316mV is the voltage at the node on the current estimation step? What is residue? It is +-43.78mV, but REF does not change.  So what is REF and RESIDUE in this case?
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Ken Kundert
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Re: oscilalting convergence residue w/ veriloga signal generator
Reply #2 - Jul 24th, 2019, 11:40am
 
You have created a limit cycle oscillation, probably with an if statement. Consider an example. Imagine modeling the output state of a charge pump driving a capacitor, and consider how you would implement voltage limiting. So when the charge pump is active it is charging the capacitor but the voltage should not go above Vdd. So you might have something like the following code:

Code:
analog begin
    Iout = 100u*u-100u*d;
    if (V(out) > V(vdd))
	  Iout = 0;
    I(out) <+ Iout;
end 


Imagine that at time point t1 V(out) is below V(vdd), then the charge pump will be active and if u is high the output current will be charging the load capacitor. Now consider that at the next time point t2 V(out) is found to be above V(dd) on the first iteration. Then on the second iteration Iout will be zero, which results in V(out) not changing from its value at t1. Thus, on the third iteration the output voltage  will be below V(dd) and the charge pump becomes active again. This process repeats forever.

In a sense what is happening is that your if statement divides the behavior into two regions: active and clipping. At t2 the if statement always tries to put the model into the opposite region. To fix this you want to implement a behavior that tends to keep you in the same region. So instead you might try something like this:
Code:
analog begin
    Iout = 100u*u-100u*d;
    if (V(out) > V(vdd))
	  I(out) <+ Iout + (V(out) - V(vdd)/100 = 0;
    else
	  I(out) <+ Iout;
end 


This basically adds a 100Ω resistor between vdd and the output when V(out) goes above V(vdd). Thus, once the if statement determines the model should be in clipping, it implements a behavior that keeps the model in clipping.

-Ken
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Horror Vacui
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Re: oscilalting convergence residue w/ veriloga signal generator
Reply #3 - Jul 24th, 2019, 2:47pm
 
Hi Ken,

Thanks for your answer. Unfortunately I am pretty sure that such oscillation is not built into the veriloga module.  It does not have any V/I characteristic like a component, it is more like a time varying voltage source and as such its output voltage can not change between iterations. I have used $display statements everywhere in the code where the amplitude or the frequency is changed, but they are not displayed in spectre's log between the convergence debug messages.

Can you confirm that the code snippet I shared corresponds to an ideal voltage source?

Just to make it easier to image what it is: It adaptively sweeps the input power and frequency based on the output frequency to determine a frequency divider's sensitivity curves. The output is changed only if either there are N consecutive periods where the divider works well, or after a long time window.

Can you help me understand the error message? I assume the simulator solve equations like Σ y(x) = 0. Can we say that x is the voltage, and y the current in general, or it is way more abstract? Is RESIDUE the iteration step around REF, which results in "Soln" current, which differs from the previous iteration value by "Delta"?
The naming might be trivial for others, but I did not learnt algebra or algorithms in English.
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Ken Kundert
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Re: oscilalting convergence residue w/ veriloga signal generator
Reply #4 - Jul 24th, 2019, 3:42pm
 
Quote:
SIM_CONTROL:Out_vss_flow (Soln = 3.03834 A Delta = 3.04431 A), residue: SIM_CONTROL:Out_vss_flow (RESIDUE= 43.7835 mV REF = 692.316 mV)


This suggests that current flowing in the (Out,vss) branch [Out_vss_flow] is not converging. That could occur if the branch voltage was changing abruptly, or it could be that the current is changing as a result of changes in the load.  The output voltage depends on out_DC, vout, and phase, the latter two of which will not change over iterations because they are the output of transition and idtmod. So, the problem could result from out_DC, or it could result from changes in the load.

Soln -- value of the independent variable proposed by the simulator on current iteration (in this case the branch current of the (Out,vss) voltage source branch)
Delta -- the difference between the previous value of Soln, and the current value.
RESIDUE -- the amount by which the equation is not satisfied. The equation for a voltage source branch has the form V(p,n) = E where p, n are the terminals and E is the drive value. Thus RESIDUE = E - V(p,n)
REF -- the reference value used to compute the tolerance from relref. Thus, for convergence |RESIDUE| < reltol*|REF|. In this case REF is probably E.

I would not put too much stake in these messages. They are often misleading.

I would also keep looking for that if statement, starting from the load. It is probably not in SIM_CONTROL.
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Ken Kundert
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Re: oscilalting convergence residue w/ veriloga signal generator
Reply #5 - Jul 24th, 2019, 3:47pm
 
Code:
phase = `M_TWO_PI*idtmod(fc,0,1,0);
V(Out,vss) <+ out_DC + vout*cos(phase); 


That code snippet looks fine. It is a good description for a VCO. However, it should be accompanied by a boundstep statement:

Code:
phase = `M_TWO_PI*idtmod(fc,0,1,0);
V(Out,vss) <+ out_DC + vout*cos(phase);
$boundstep(0.1/fc); 


It won't help you convergence issues, but it will prevent you from violating the Nyquist constraint.

-Ken
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Horror Vacui
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Re: oscilalting convergence residue w/ veriloga signal generator
Reply #6 - Aug 15th, 2019, 4:10am
 
I was able to solve the problem by simplifying the layout used for extraction. Unfortunately I was not able to pinpoint anything in the design which has caused the issue.

Many thanks for your help and explanations, Ken!
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