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Mar 29th, 2020, 11:57am
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IP3 Simulation of a Sample and Hold Circuit in Spectre (Read 38 times)
repah
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IP3 Simulation of a Sample and Hold Circuit in Spectre
Mar 26th, 2020, 10:32pm
 

I want to measure the IP3 of a Sample and Hold (clocked) using Cadence Spectre.

What is the best procedure for this ? QPSS or PSS ?

I want to sweep over input voltage.

The circuit diagram is attached.  Just a simple tgate switch with a hold cap clocked at 2GHz, followed by a buffer then another tgate switch and a hold cap.

Input is a 50Mhz sine wave at 5mV.

Do I follow advice in application note - simulating switched capacitor filters on this forum - ie. do QPSS ?  How is this setup for a clock and an rf input, if using QPSS ?

Thank you.
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Ken Kundert
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Re: IP3 Simulation of a Sample and Hold Circuit in Spectre
Reply #1 - Mar 27th, 2020, 10:31am
 
From a simulators perspective, a clocked sample and hold is no different from a mixer where the clock plays the role of the LO.

I recommend you following the instructions in Accurate and Rapid Measurement of IP2 and IP3. See section 7.

-Ken
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repah
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Re: IP3 Simulation of a Sample and Hold Circuit in Spectre
Reply #2 - Today at 1:34am
 
Thank you Mr. Kundert.

But this system is clocked, do I use a SINE for my LO (clock port in sampling application) versus a PULSE.

I notice when simulating mixers - the LO is defined as a SINE even though it is a pulse.

Why is this ?

Also following the example in your application note:

My LO is the clocking frequency of the sample and hold, say 50MHz.

My f1 is the input frequency of the sample and hold, say 2GHz.

I use 51MHz as an f2.

In QPSS, I set LO to be large signal and f1 to be moderate.

Then in QPAC I set my f2 to be 51MHz.

I do this, and I don't get a reasonable response, but I used PULSE on my ports for clock/lo and not SINE.

What am I doing wrong ?
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