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Trade-off between LDO max Iout AND PSRR (Read 824 times)
blue111
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Trade-off between LDO max Iout AND PSRR
May 16th, 2020, 9:21am
 
PSRR is inversely proportional to output impedance of LDO.

But Iout_max of LDO is proportional to width of output mosfet (M20) , Rds of M20 is inversely proportional to width of M20.

Given that output impedance is a parallel impedance configuration between Rds of M20 and (R1+R2), so Iout_max is proportional to output impedance of LDO.

If I need Iout_max = 3A, then my PSRR result looks very very bad.









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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #1 - May 18th, 2020, 4:41am
 
To understand your problem:
- Vin = 1V
- non-inverting opamp configuration with gain = 2 V/V. Hence, desired Vout = 2V

What do you need next? You need output quiescence DC current equal to 3A?
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #2 - May 18th, 2020, 4:54am
 
I have done some more modifications.

Please find attached the latest circuit at the end of this post.

I just wish to improve the PSRR which is only around 45dB

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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #3 - May 18th, 2020, 5:42am
 
blue111 wrote on May 18th, 2020, 4:54am:
I just wish to improve the PSRR which is only around 45dB


OK, but PSRR may have many sources. What I recommend is to find them. In order to do so, plot not only Vout but other voltage points and currents and verify if their changes due to power supply Vin are as expected or too big.
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #4 - May 19th, 2020, 1:49am
 
The gate voltage fluctuation due to Vin for both M10 and M18 are a bit large.

Any advices ?
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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #5 - May 19th, 2020, 2:23am
 
blue111 wrote on May 19th, 2020, 1:49am:
The gate voltage fluctuation due to Vin for both M10 and M18 are a bit large.


That's a good point. M10 is a current source of the input differential pair. Try to put a capacitor there to stabilize that node and check your PSRR.

Moreover, I investigated your schematic. You used minimum length transistors, that is L=0.18um. Cannot you increase lengths of transistors? That should help for PSRR, especially if you increase lengths of PMOS transistors. Power supply variations are directly on sources of PMOS transistors. The longer PMOS transistors, the less sensitive PMOS transistors are on power supply variations.
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #6 - May 19th, 2020, 2:44am
 
Putting a small 10pF capacitor to smooth out the gate voltage fluctuation for M10 only increases PSRR by 1dB

I cannot put large capacitor because it will upset the bode plot entirely due to extra pole created by the extra capacitor.

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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #7 - May 19th, 2020, 3:31am
 
blue111 wrote on May 19th, 2020, 2:44am:
Putting a small 10pF capacitor to smooth out the gate voltage fluctuation for M10 only increases PSRR by 1dB

Sorry. Put this capacitor between gate and source of M10.


blue111 wrote on May 19th, 2020, 2:44am:
I cannot put large capacitor because it will upset the bode plot entirely due to extra pole created by the extra capacitor.

No. Gate of M10 is not in the feedback path.


What about minimum length transistors? Do you need to use them?
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #8 - May 19th, 2020, 3:57am
 
I just put a 10F capacitor between gate and source of M10, but it only increases PSRR by 1dB.
So, I believe PSRR had to be improved by some other ways.

I suppose 0.18um (180nm) channel length is already quite "long" compared to 7nm now ?

I only modify L for the two branches of the bias circuit at the leftmost of the circuit

when I used L=1.8u, PSRR again only increases by 1dB

when I used L=18u, PSRR drops to 30dB
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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #9 - May 19th, 2020, 4:33am
 
blue111 wrote on May 19th, 2020, 3:57am:
I just put a 10F capacitor between gate and source of M10, but it only increases PSRR by 1dB.

10pF capacitor between gate M10 and ground increases PSRR by 1dB and 10F (!) capacitor between gate and source of M10 increases PSRR by 1dB? Is that correct?


blue111 wrote on May 19th, 2020, 3:57am:
So, I believe PSRR had to be improved by some other ways.

Capacitors between gate and source of PMOS transistors as well as increasing length of PMOS transistors are common techniques to increase PSRR. If you understand PSRR then you understand why these techniques work and how they help.


blue111 wrote on May 19th, 2020, 3:57am:
I suppose 0.18um (180nm) channel length is already quite "long" compared to 7nm now ?

These are different technologies: 180 nm vs 7 nm. I do not know how would you like to compare them.
Have you ever done 7nm analog design? Please tell me, that you designed any bandgap or opamp using minimum length transistors in 7 nm, 16 nm, 28 nm or any "modern" technology ...

blue111 wrote on May 19th, 2020, 3:57am:
I only modify L for the two branches of the bias circuit at the leftmost of the circuit

when I used L=1.8u, PSRR again only increases by 1dB

when I used L=18u, PSRR drops to 30dB

But you do not know where is the main source / sources of PSRR. Moreover, by increasing length of only M6 and M2 you do not have matching anymore between M6 and M9 transistors as well as M6 and M10 transistors. What is your experience in analog design? Why have you taken such complicated architecture without experience?

What is one of the best things you can do right now is to delete all current source reference block and bias with desired constant current M10 and M9 transistors.
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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #10 - May 19th, 2020, 4:34am
 
this post is required to be deleted, please
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #11 - May 19th, 2020, 5:05am
 
the 10pF capacitor was between gate and ground.

the 10uF capacitor was between gate and source (Vin).

The result I posted in previous post was only for 10uF capacitor.

What do you exactly mean by delete all current source reference block and bias with desired constant current M10 and M9 transistors ?

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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #12 - May 19th, 2020, 6:02am
 
blue111 wrote on May 19th, 2020, 5:05am:
the 10pF capacitor was between gate and ground.

the 10uF capacitor was between gate and source (Vin).

This is what I wrote. Just except, previously you had written about 10 F capacitor not 10 uF.
Thank you for confirmation.

blue111 wrote on May 19th, 2020, 5:05am:
The result I posted in previous post was only for 10uF capacitor.

Yes, I understood it that way. Thank you for this to make the thing clear.

blue111 wrote on May 19th, 2020, 5:05am:
What do you exactly mean by delete all current source reference block and bias with desired constant current M10 and M9 transistors ?

M1-M6 and R3 generate the bias current. Hence, Current Source Reference (CSR) block. Delete all of this and put DC current with one diode-connected transistor (you may keep M6). Simulate and tell your results.
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #13 - May 19th, 2020, 7:34am
 
If I use an ideal current source instead of Current Source Reference (CSR) block, PSRR only improves by around 1dB

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Re: Trade-off between LDO max Iout AND PSRR
Reply #14 - May 20th, 2020, 2:12am
 
blue111 wrote on May 19th, 2020, 7:34am:
If I use an ideal current source instead of Current Source Reference (CSR) block, PSRR only improves by around 1dB


Great. We are going ahead. So for CSR we have only M6 right now.

Have you investigated? What are the nodes/currents that changes a lot due to power supply variations? Maybe:
- ID_M10 ?
- voltage on drains of M7/M17 what leads to changes on M20 gate?

Are you aware that your output transistor is 48.000/0.18 um= 48 mm / 0.18 um = 4.8 cm / 0.18 um ?
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