blue111 wrote on May 19th, 2020, 3:57am:I just put a 10F capacitor between gate and source of M10, but it only increases PSRR by 1dB.
10pF capacitor between gate M10 and ground increases PSRR by 1dB and 10F (!) capacitor between gate and source of M10 increases PSRR by 1dB? Is that correct?
blue111 wrote on May 19th, 2020, 3:57am:So, I believe PSRR had to be improved by some other ways.
Capacitors between gate and source of PMOS transistors as well as increasing length of PMOS transistors are common techniques to increase PSRR. If you understand PSRR then you understand why these techniques work and how they help.
blue111 wrote on May 19th, 2020, 3:57am:I suppose 0.18um (180nm) channel length is already quite "long" compared to 7nm now ?
These are different technologies: 180 nm vs 7 nm. I do not know how would you like to compare them.
Have you ever done 7nm analog design? Please tell me, that you designed any bandgap or opamp using minimum length transistors in 7 nm, 16 nm, 28 nm or any "modern" technology ...
blue111 wrote on May 19th, 2020, 3:57am:I only modify L for the two branches of the bias circuit at the leftmost of the circuit
when I used L=1.8u, PSRR again only increases by 1dB
when I used L=18u, PSRR drops to 30dB
But you do not know where is the main source / sources of PSRR. Moreover, by increasing length of only M6 and M2 you do not have matching anymore between M6 and M9 transistors as well as M6 and M10 transistors. What is your experience in analog design? Why have you taken such complicated architecture without experience?
What is one of the best things you can do right now is to delete all current source reference block and bias with desired constant current M10 and M9 transistors.