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May 21st, 2024, 11:06pm
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Charge Redistribution DAC caliberation (Read 639 times)
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Charge Redistribution DAC caliberation
May 31st, 2020, 6:04am
I am designing a charge redistribution DAC for a 5-bit SAR ADC. All my components (including comparator, capacitors and logic gates) are ideal veriloga blocks from ahdl library of cadence. I've designed only the switches using tsmc 180 nm technology. They are normal transmission gate two-way switches.

The MSB is getting set at exactly half of the voltage range i.e. I'm getting till 10000 with error < 1/2LSB. But further lesser significant bits show error in the upper half voltage range and the conversion doesn't go above 11010 for full range. How do I calibrate my results?

I've used capacitors (3.4pF, 1.7pF, 850fF, 425fF, 212.5fF and 212.5fF). Do I need to design separate switches for each capacitor? And how would varying transistor sizes affect the voltage levels in capacitor array?
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