Hello,
I am trying to implement something like the deepprobe function that is provided by Cadnece, but with veriloga only, as I use HSPICE. The idea is to be able to probe a net in a sub-block without having to pin that net out to the top level.  Right now I have some code like this, but the output just reads some mV and does not track the internal net.

Code:

`include "constants.vams"
`include "disciplines.vams"

module deepprobe_ams (out);

output out;
voltage out;
//parameter string hiername = "tbname.I1.I0.c";
analog begin
	V(out) <+ V(xtb.clk10x_h);
end

endmodule 

a few questions:

• Can I make a string parameter that can be filled in for the probe path like in deepprobe?
• should the hierarchical naming be in relation to where the veriloga block is instantiated in the hierarchy or relative to the SPICE deck?

I have consulted the Accellera language reference manual, and have not had any luck.

BTW, I have The Designer's Guide to Verilog AMS book, and I find it is very well written.  Thanks for that.