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Apr 17th, 2021, 7:20am
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How to export a bunch of variables to digital by an ADC template in Veriloga-A (Read 121 times)
Tesla
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How to export a bunch of variables to digital by an ADC template in Veriloga-A
Feb 25th, 2021, 6:51am
 
I have a module that generates a bunch of variable values, then I want to export each one of them in digital format to output. The complication is that I want to use a single ADC template and instantiate it multiple times. I am now stuck at assign proper type for whatever goes to adc as input to be quantized.

More specifically, below is the example (I modified the adc module from the bible "THE DESIGNER’S GUIDE TO VERILOG-AMS". I removed the clk signal and add vdd and gnd pin.)
Apparently, "wire out1_internal" is not the correct declaration. Nor is "reg out1_internal"

module adc(vdd, gnd, in, out);
   parameter integer bits = 64 from [1:64];      // resolution (bits)
   parameter real fullscale = 1.0;      
   parameter real td = 0;            // delay from clock edge to output (s)
   parameter real tt = 0;            // transition time of output (s)
   parameter integer dir = 1 from [-1:1] exclude 0;                              
   input in, vdd, gnd;
   output [0:bits-1] out;
   voltage in; voltage vdd; voltage gnd;
   voltage [0:bits-1] out;
   real sample, midpoint;
   integer result[0:bits-1];
   genvar i;
     real vdd_;
     real      thresh;

   analog begin
     @(initial_step) begin
           vdd_=V(vdd,gnd);
           thresh=vdd_/2;
         sample = V(in);
         midpoint = fullscale/2.0;
         for (i = bits - 1; i >= 0; i = i - 1) begin
           if (sample > midpoint) begin
               result[i] = 1;
               sample = sample - midpoint;
           end else begin
               result[i] = 0;
           end
           sample = 2.0*sample;
         end
     end
     for (i = 0; i < bits; i = i + 1) begin
         V(out[i]) <+ transition(result[i] ? vdd_: 0.0, td, tt);
     end
   end
endmodule

`define n_bits_out1 4
`define n_bits_out2 6
module some_module(vdd, gnd, out1, out2)
input vdd, gnd;      electrical      vdd, gnd;
output [`n_bits_out1:1] out1; electrical [`n_bits_out1:1] out1;
output [`n_bits_out2:1] out2; electrical [`n_bits_out2:1] out2;
integer var1, var2;
wire out1_internal;
wire out2_internal;
analog begin      
 @ ( initial_step ) begin
     var1=10;
     var2=50;
    end
V(out1_internal) <+ var1;
V(out2_internal) <+ var2;
end
adc #(.bits(`n_bits_out1)) adc_var1(vdd, gnd, out1_internal, out1);
adc #(.bits(`n_bits_out2)) adc_var2(vdd, gnd, out2_internal, out2);
endmodule

Thanks

=====================
Update:
Correct me if I am wrong, but it seems "electrical out1_internal" is the correct syntax for this purpose.
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« Last Edit: Feb 26th, 2021, 3:36am by Tesla »  
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Tesla
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Re: How to export a bunch of variables to digital by an ADC template in Veriloga-A
Reply #1 - Mar 2nd, 2021, 1:52am
 
I confirm that "electrical out1_internal" is the correct syntax to declare.
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Ken Kundert
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Re: How to export a bunch of variables to digital by an ADC template in Veriloga-A
Reply #2 - Mar 2nd, 2021, 1:56pm
 
Are you asking how you should drive the digital pins of your ADC from your testbench?
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