A simple periodic pulse generation :
1. Pulse repeats with period = clkPeriod.
2. A timer generated clkIn produces a clk whose rising edge is used to initiate the pulse, 'tLaunch' away from the clkIn edge.
3. Pulse is deasserted 'tRemove' away from the time of launch.
4. tLaunch + tRemove is ensured to be less than clkPeriod.
Code:<verilogA>..
//Clock Generation
@(timer(nextEdge)) begin
clkIn = 1-clkIn;
nextEdge = nextEdge + 0.5*clkPeriod;
end
//Launch of pulse
@(timer(nextEdge+tLaunch)) begin
pulse = 1;
end
//Deassertion of pulse
@(timer(nextEdge+tLaunch+tRemove)) begin
pulse=0;
end
The above code doesn't produce the pulse. But there is a code change that can produce the pulse which I don't understand why.
Code://Clock Generation
@(timer(nextEdge+extraTime)) begin ... end
Could you please help in understanding what the issue is? This extraTime needs to be greater than the 'tLaunch' when I tried tweaking it.