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May 21st, 2024, 9:43pm
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LNA tail current biasing (Read 652 times)
Junior Member

Posts: 12

LNA tail current biasing
Oct 21st, 2021, 4:09am

I am designing an LNA with bias current fixed through NMOS tail current.  How should the gate voltage of this tail current NMOS be generated so that LNA characteristics do not shift with PVT (process voltage temp.)  shifts.
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Horror Vacui
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Posts: 127
Dresden, Germany
Re: LNA tail current biasing
Reply #1 - Mar 14th, 2022, 7:35am
Oh, boy! That's the holy grail of analog IC design.

Basically you need to develop a function for all parameters you are interested in as a function of PVT. Then your circuit needs to determine which PVT condition you are in, and then you correct the tail current with an inverse of the above mentioned functions.

Issue #1: different parameters have a different PVT dependence.
Issue #2: the interdependence of difference blocks makes things way too complicated for any analytical treatment. (--> here comes the art part, which is nothing else than the intuition of experienced colleagues)
Issue #3: the circuit should be capable to measure the PVT corner it is currently in.
Issue #4: implementation of the inverted functions are rarely trivial even with a lookup table, unless limited gain is accepted.

Usually voltage dependence can be eliminated with self-biased references.
For one parameter you can build a reference unit and compare the performance of your circuit to it, and correct the difference with a loop. The issue is that it is not easy to implemented on an chip reference. Any off-chip calibration is limited and will take time at the manufacturing, or it will require some special BOMs later in the PCB.

Note, that added complexity increase design time, silicon area, verification complexity, failure modes, power consumption, noise and disturbances in your system.
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