I'm currently developing some Verilog-AMS models for analog circuits, in which I'm modelling analog signals using wreal types. So a typical module might look like the following:
Code:

module myblock ( vin,  iout );
  input vin;
  wreal vin;
  output iout;
  wreal iout;
  (...)
endmodule 

I'm simulating these blocks both on top level, where all blocks are wreal models, and on block level, where this block will be used in a schematic view with Spectre components.

In the latter case, I need to set up the interface elements correctly. The difficulty is that some pins operate in voltage mode while others operate in current mode. That means the interface elements need to have different settings in each case, mainly in the currentmode setting.

In the Xcelium command-line flow, I could define something like this in my amscf.scs:
Code:

amsd {
        ie vsup=1.8 cellport="myblock.vin" currentmode=0
        ie vsup=1.8 cellport="myblock.iout" currentmode=1
} 

In ADE, I would go to the Interface Element Setup window and select each pin to define the scope, then set the correct options.

However, in each case I have to point specifically at each pin to tell the simulator what type of IE it needs. This is very cumbersome and error-prone in a large design where there might be dozens of pins. Is there a way to define something in the Verilog-AMS code that will tell the simulator what type of IE needs to be inserted? For example, to define pins as wreal_v and wreal_i? Or can I somehow tell the simulator to use different settings for pin names starting with "i"?