DenisMark
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In detail: // Verilog-AMS netlist generated by the AMS netlister, version 5.0.33_USR1.35.4. // Cadence Design Systems, Inc.
`include "disciplines.vams" `include "constants.vams" module test ( ); resistor #(.r(1K)) (* integer library_binding = "analogLib"; *) R0 ( cds_globals.\gnd! , net1 ); generator (* integer library_binding = "testlib"; *) I0 ( .aout( net1 ), .ref( cds_globals.\gnd! ) );
endmodule
This is test VHDL-AMS generator description: library ieee, std; use ieee.std_logic_1164.all; use ieee.electrical_systems.all;
entity generator is generic ( ULO : real := 0.2; -- output voltage for logic '0' UX : real := 2.5; -- output voltage for logic unknown or high-impedance UHI : real := 4.8; -- output voltage for logic '1' RON : real := 0.1; -- internal resistance for strong states RWK : real := 1.0e4; -- internal resistance for weak states ROF : real := 1.0e9; -- internal resistance for high-impedance state TT : real := 1.0e-9); -- output transition time port ( terminal aout, ref: electrical); -- analog outputs end generator;
architecture bhv of generator is type real_table is array (std_logic) of real; constant R_table: real_table := (RON, RON, RON, RON, ROF, RWK, RWK, RWK, ROF); constant V_table: real_table := (UX, UX, ULO, UHI, UX, UX, ULO, UHI, UX); quantity uout across iout through aout to ref; signal reff: real := 0.0; -- effective resistance signal veff: real := 0.0; -- effective voltage signal din: std_logic := '0'; -- logic input begin din <= not din after 10us; reff <= R_table(din); veff <= V_table(din); uout == veff'ramp(TT) + iout*reff'ramp(TT); -- iout is defined from aout to ref end architecture bhv;
Thanks...
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