Hi,

right now I don't have access to Baker's book, but I have the following hypothesis. In the first case, your increment from sample to sample is relatively small (as you are doing a tri-wave sweep), so the charge the S&H has to deliver during each cycle is small. In the second case, the charges on the input capacitor of the second stage are transfered to the hold capacitor once a period, i.e. the capacitor is discharged when it is connected back to the output of the first stage. If this is the case (please confirm), then the amount of the charge the S&H has to deliver each clock cycle is much smaller and the slew-rate current of your FC OTA may be too small. Would this apply to your case?

As pipeline ADCs are Nyquist-rate converters, you must check the SR performance of the S&H. You cannot expect having slowly varying input signals as in oversampled converters.

Paul