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Sid

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Simulating ADC INL, DNL and FFT Spectrum
Jun 02^nd, 2005, 7:56am

Hi,

I have built a 12-bit ADC in Cadence. So far I have been simulating it with a ramp input and checking that the codes increase monotonically at the speed of interest. However, even for checking about 30 continuous codes the simulation takes 12 hrs due to the large size of the pipeline ADC.

How do I simulate it's INL, DNL and FFT spectrum within a reasonable simulation time?

Any help will be greatly appreciated.

Thanks,
Sid

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sheldon

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Posts: 751

Re: Simulating ADC INL, DNL and FFT Spectrum
Reply #1 - Jun 2^nd, 2005, 8:53pm

Sid,

Could you provide some details about your circuit and simulation
setup? For example, does the simulation include back-annotated
parasitics? Power supply parasitics? etc? My expectation is that
a for a circuit level simulation of a 256 point FFT for a 10bit
Pipeline ADC should take about 6 hours on good harware,
Opteron. For older hardware SUN UltraSPARC, the time
will be closer to 20 hours. If you setup the simulation correctly,
you should be able to get ~100dB of dynamic range, for a 0dB
input the FFT noise floor should be down at -100dB. This should
be enough sufficient for most 10-12 ADCs.

INL and DNL are really tough to simulate since you need to
exercise each bit several times. One strategy is to run the FFT
simulation at a low input frequency an calculate the INL from
the SFDR.

Best Regards,

Sheldon

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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: Simulating ADC INL, DNL and FFT Spectrum Reply #2 - Jun 2^nd, 2005, 11:46pm Sheldon, I am interested in the method that you mentioned to measure INL. Quote: One strategy is to run the FFT simulation at a low input frequency an calculate the INL from the SFDR. Would you please explain it in detail? How much points does it need to calculate INL from the SFDR? Thanks Yawei
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sheldon Community Fellow Offline Posts: 751	Re: Simulating ADC INL, DNL and FFT Spectrum Reply #3 - Jun 5^th, 2005, 6:33pm Yawei, There is a short summary at : www.stanford.edu/class/ ee315/handouts/h05_lecture3_2.pdf see page 35. Let me know if you need more detail, I have more other references. Best Regards, Sheldon
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Leyman Junior Member Offline Posts: 11 Malaysia	Re: Simulating ADC INL, DNL and FFT Spectrum Reply #4 - Jun 30^th, 2005, 8:47pm Sheldon, I could not get the document from stanford website regarding simulation INL/DNL? Do you mind sharing the documents? Any other good reading material on INL/DNL simulation? You can sent the document to: snoop835@hotmail.com Thank you in advance -leyman-
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jbdavid Community Fellow Offline Posts: 378 Silicon Valley	Re: Simulating ADC INL, DNL and FFT Spectrum Reply #5 - Oct 3^rd, 2005, 11:14pm I also addressed that in my tutorial on Pipeline converters on the 2002 BMAS www.bmas-conf.org along with a number of paper references back to the classic papers that outline that methodology for testing ADC's.. jbd
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Sid Community Member Offline Posts: 35	Re: Simulating ADC INL, DNL and FFT Spectrum Reply #6 - Oct 4^th, 2005, 8:20am David, Exact paper name please? Thanks, Sid
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sheldon Community Fellow Offline Posts: 751	Re: Simulating ADC INL, DNL and FFT Spectrum Reply #7 - Oct 4^th, 2005, 6:42pm Greetings, Please look at the following paper, " FFT test pf A/D Converters to Determine the Integral Nonlinearity", Francesco Adamo, et. al., Transactions on Instrumentation and Measurement technology, Vol 51. No 5., October 2002, page 1050-1054 Best Regards, Sheldon
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jbdavid Community Fellow Offline Posts: 378 Silicon Valley	Re: Simulating ADC INL, DNL and FFT Spectrum Reply #8 - Oct 5^th, 2005, 4:59pm Maybe I shouldn't wait for David to answer since the question seemed to be for me ::) http://www.bmas-conf.org/2002/index.html Look for: Modeling and Test Bench Generation: A Case Study with Pipelined A/D Converters (paper 630KB) Jonathan David ― Cadence Design Systems, USA HTH jbdavid
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