as someone who has been using AMS Designer since it first was released in early 2000, I'll suggest that AMS is better for verification than a co-sim solution..
for background info that is NOT on this website (but managed by the Same Guys) .. look at
www.bmas-conf.org lots of good background papers there
but the primary advantage of AMS is that most of the design is netlisted as a Verilog(AMS) netlist.. which gives you all the features of Verilog-2001 (some of 1364-2005) as well as the Analog extensions.. meaning that you can write models to check analog outputs and integrate them with your normal digital verification environment.
Of course the best approach is to start developing your top level testbench using VERY FAST behavioral models.. and then as the schematics finish up and go to layout, you can substitute them in and run enough spot checks to validate that the models are correct..
(not all of them at once.. as that might make the simulation very slow. )
Commonly this issue is raised when the design is done, and spending a n additional 2-3 months learning Verilog, VerilogAMS and writing models is not palatable to management. At this point you won't get the same design/functional coverage as you would with the first approach, but you can run an effective RTL + transistor level sim ulation in a FAST spice type simulator..
AMSUltrasim is one -- and there are other alternatives, some of which can use the Verilog + spectre netlists you are using today.
and if the analog parts aren't too big, you can even run a tolerable (couple of days or a week or so) run in AMS(Spectre)
--
Hoping you're not in that boat..
jbd