VerilogAMS is pretty fine for that purpose.
You could also use VHDL-AMS or SystemC-AMS but to my knowledge, VerilogAMS is much better understood by most analog designers

If you plan to use any behavioral analog models, you should consider how you will certify that the models and their circuit counterparts behave the same. If your circuits are implemented in the Cadence environment, I would use VerilogAMS. VerilogAMS is Cadence's flagship modeling language.

Hi,

Thank you all for replies.  Basically our flow is RTL (Verilog)  and Analog Portion is Schematic composer.

I have one question related to Verilog AMS flow: Does the analog portion required an additional view from foundry?

If yes, what is the view name? what is it called ?  (Why is it needed)

as someone who has been using AMS Designer since it first was released in early 2000, I'll suggest that AMS is better for verification than a co-sim solution..
for background info that is NOT on this website (but managed by the Same Guys) .. look at www.bmas-conf.org  lots of good background papers there
but the primary advantage of AMS is that most of the design is netlisted as a Verilog(AMS) netlist.. which gives you all the features of Verilog-2001 (some of 1364-2005) as well as the Analog extensions.. meaning that you can write models to check analog outputs and integrate them with your normal digital verification environment.

Of course the best approach is to start developing your top level testbench using VERY FAST behavioral models.. and then as the schematics finish up and go to layout, you can substitute them in and run enough spot checks to validate that the models are correct..
(not all of them at once.. as that might make the simulation very slow. )

Commonly this issue is raised when the design is done, and spending a n additional 2-3 months learning Verilog, VerilogAMS and writing models is not palatable to management. At this point you won't get the same design/functional coverage as you would with the first approach, but you can run an effective RTL + transistor level sim ulation in a FAST spice type simulator..
AMSUltrasim is one -- and there are other alternatives, some of which can use the Verilog + spectre netlists you are using today.
and if the analog parts aren't too big, you can even run a tolerable (couple of days or a week or so) run in AMS(Spectre)
--
Hoping you're not in that boat..
jbd

Yes thats what I mean..
--
there is little "trusting" curve for the analog designers.. once you get the netlisting working right, since the analog simulation engine is still spectre.
There are a lot of mixed signal designs that don't need anything more than spectre-Verilog .. but I have been lucky enough not to work in those domains for the last 7 years.
PLL's are one area where the true mixed signal capability shines..
--good luck