Hi there,
Sorry for the delay, I was out of office for some days.
@Alexandar: Yes, two stages indeed. I will follow your suggestion and analyze the CMFB loop separately. I will try to break the CMFB loop somewhere to apply some open-loop phase margin analysis. Thanks.
@Wave: Yes, it is now very clear to me that the CMFB loop will likely have one additional stage w.r.t. the diff amp. However, I am a bit confused with your comments. The main amp already has independent PMOS current sources. If I added another current source at the NMOS end, the circuit would have one bias source too many. I have seen somewhere that another independent current source may be added in parallel with the NMOS current sources driven by the CMFB amplifier. While that reduces the gain of the CMFB loop, which, in turn, improves the stability, I never thought of start-up issues with this circuit. Would you please elaborate your concern with start-up issues?
I am also confused with your second suggestion. I think you are suggesting to use diode-connected loads for the CMFB amp, which also reduces its DC gain quite significantly. Is my understanding right ? Thanks.
I think that having a high DC-gain but correctly compensated CMFB amplifier is a more appropriate design approach. However, if anyone already sees a flaw in my reasoning (and schematic), please let me know. I don't want have bad surprises when my silicon is back 6 months from now...