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Simulating the effect of phase noise (Read 1818 times)

xtal New Member Offline Posts: 5 Salt lake city	Simulating the effect of phase noise May 25^th, 2012, 12:41am Hi all, I want to study the effect of phase noise on my circuit performance. Is there a way I could create a source (signal generator) where I can give the phase noise number I want and then use it for simulation? Any helpful pointers would be greatly appreciated. Manohar
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ACWWong

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Oxford, UK

Re: Simulating the effect of phase noise
Reply #1 - Jun 7^th, 2012, 9:27am

Assuming you are using Cadence, then there is a library as part of the installation called rfLib. Inside there there is a cell called vco which is a verilogA model of what you want.

Other options are to write your own model. You can get ideas on this website:

http://www.designers-guide.org/VerilogAMS/functional-blocks/vco/vco.va

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