ywguo
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Hi,
I have got a little problem in designing the reference voltage buffer for 10 bits - 40M, pipeline A/D converter, and hope you could help me for better understanding.
As you know, the voltage references in an SC data converter need to charge and discharge a capacitor, so to achieve very high speed and resolution from a pipeline A/D converter, the MDAC reference voltages (their values are 2.1v, 1.1v for my application) must be buffered in order to attain the required accuracy and settling time. My reference voltages (their values are 2.1v, 1.1v for my application) are generated by an on-chip bandgap reference.
The problem came up when I was making the specification for my buffer of the MDAC reference voltages. I plan to realize my buffer by using a three-stage cascade operational amplifier in feedback in order to provide low output impedance. And the problem is I am just not sure how much the unity-gain bandwidth my buffer needs. Especially when I want to use a buffer combined with an external stabilization capacitor.
The reasons I am not sure about the unity-gain bandwidth are:
1, I think we just need to buffer a dc voltage (like 2.1v), so I don’t think the buffer should be fast.
2, When I use an external stabilization capacitor, apparently the speed of the buffer is slowed down, but the variations at the output of the buffer seemed to be decreased.
So I am really puzzled, I am really not sure how much the unity-gain bandwidth my buffer needs when I use a huge external stabilization capacitor.
I hope you could help me to get a little more insight.
Best regards, Yawei Guo
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