i am designing a PLL circuit for the tuning circuit for a gm-C filter.
i design a third order PLL, where the second order loop filter is used.
i have searched through the literature, there are a lot of PLL theory, design etc. However, none about the design specification about the tuning circuit with PLL.
I have a few problem,
1.) how to estimate the settling time of the PLL? i simulate the PLL with transient simulation, and check the loop filter output, it gives me the settling time. But, what parameters in the derivation of the transfer function of the PLL determine the settling time in third order, or forth order, and even the second order?
2.) i estimate the tuning range of the filter from the VCO sensitivity, may i do in this manner?
3.) i use the control signal of the VCO to control the filter, than how to determine the noise inject into the filter? many PLL literature discuesses the noise after the VCO, for synthesiser. How's the effect of the phase noise? jitter etc. is it phase noise and jitter are the same?
4.) how large the lock/capture range required? how to estimate the lock/capture range? if can't be manual estimate, how to simulate this condition? i try to change the reference frequency and than check whether it will be locked, but not yet got any conclusion?
5.) is that the reference frequency suppression using forth order loop filter is required here. i guess no, but is it truth?

Thanks.