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jason_class

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Folded cascode and slew rate
Sep 08^th, 2003, 11:47pm

Hi All

I do not understand something from a book.

From book, it is said that Q12 and Q13 is added to counter the slew rate for this folded cascode amplifier. Kindly see the folowing page

http://www.geocities.com/jason_class/ad_folded_cascode.gif

When Q1 turn on while Q2 turn off, the foloowing is true.
ID1= 2IB
ID11 =Ibias1 + ID12 =ID3
I do not know how do we get ID11=Ibias1 + ID12.
Can you help me to understand this? Can you give me an idea how to analyse the current at drain node of Q3(considering Q11 , Q12 , Q3 and Q1 current)? I am confused with the addition of Q12 with its gate has the same bias with Q3 and Q4, why this need to be added to counter slew rate and how it manage to do so?

Then ID4=ID11=Ibias1 + ID12
Why ID4 =ID11?
WHy not ID4 = Ibias1 + ID13
Can you guide me how to analyse the current at drain of Q4(considering current from Q11, Q13, Q4 ad Q2)?
Thank you,

best regards
Jason

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Paul

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Switzerland

Re: Folded cascode and slew rateIbias+
Reply #1 - Sep 10^th, 2003, 5:06am

Hi Jason,

I must admit that I have never seen this schematic before, although I know the folded cascode (FC) amplifier quite well. I would be interested in having the book reference...

When trying to understand slew-rate workarounds, first try to understand the behavior of the circuit without these. I guess you do understand the FC correctly. One main drawback of this amplifiers drawback is the fact that its maximum output current (slew-rate current) is equal to 2Ib (if you neglect Q12 and Q13). In that case Ibias=2Ib. It is important to notice that Q12/13 are NMOS => I12/13 /= I3/4!

In order to increase the slew-rate, you must add some adaptive bias current to the circuit. In any situation, you always have, supposing all your transistors are saturated:
I11=Ibias+I12+I13
I3=I4=I11 (same gate and source voltages)

Your equations are derived from this supposing that one or the other of Q1/2 is off. Now let's take your first case: Q1 turn on while Q2 turn off.

Due to the higher drain current, the drain of Q12 is pulled down. Q12 starts injecting current to that node, increasing at the same time I11 and lowering the gate voltage. As Q2 doesn't draw any current, its drain is high (close to the supply) and Q13 is off. That's why I13 is neglected in the first equation of I11. Lowering the gate of Q11 increases the current in Q3 and Q4, increasing at the same time the available output current.

Now comes one point which isn't totally clear to me (can anyone help?) : if you increase both I3 and I4, the output current is only increased as the difference of both. In my opinion it would be preferrable to act only on the branch where the slewing current is really needed.

Paul

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jason_class

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Re: Folded cascode and slew rate
Reply #2 - Sep 10^th, 2003, 10:03am

Hello Paul

Thank you very much for answering my enquiries. It is so kind of you. If you are interested in the book, it is called Analog Integrated Circuit Design by David A Johns and Ken Martin which is which is a good book. Kindly refer to page 266. There are explanation there. Just I could not get the expalanation even after reading a few times.
Paul, I will read and check out your answers. Will write back here. Thank you for your help.

best regards and thanks
Jason_class

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Paul

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Re: Folded cascode and slew rate
Reply #3 - Sep 23^rd, 2003, 6:45am

Hi Jason,

sorry for the late reply, I was on a trip for a couple of days... This is indeed a very good book. I guess I cannot add many comments to my previous post and what is said in the book. The clamping effect mentionned first in the book reduces the time of slewing back to the operating point once the transient is over.

Just one thing to my open question: the authors assume Ibias2 being larger than Id3 (which is not always the case, in some designs they can be approximately equal). In that case, the additional current delivered by Q3 is absorbed in Ibias2. Then the I4 increase is really an increase in slewing current.

I don't know your level of expertise, but if the books explanations (quite exhaustive) don't help you get the picture I would suggest you to have a face to face discussion with an experienced analog designer.

Good luck

Paul

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fehler

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Re: Folded cascode and slew rate
Reply #4 - Sep 22^nd, 2004, 7:57am

for ID11=Ibias1 + ID12, it is very clear. When slew happens, the tail current flows through Q1, and Q1's
drain voltage will be lower, than Q12 opens. Now part
of tail current flows into Q12 and then Q11. So, now
the ID11 will be sum of Ibias1 and ID12.

In this way, the vgs of Q11 will be increased and so do
the current of Q3 and Q4. This is a transient process,
the extra current of Q3 and Q4 will be fed into the load.

Paul:

In this process, not both the current in Q3 and Q4 are
enlarged. For one of them will be shut down, with its
drain voltage too close to VDD.

In the reverse dir, the same happens.

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