I am Raymond, an analog design engineer in a fabless IC design house located in Singapore.  Right now I have encountered a problem in doing SpectreRF simulation, I need your guide and help. Sorry for taking your precious time.

Here is my story.


0) I have a VCO project from my customer.

Specification

Center Frequency: 10MHz

Phase Noise: -90dbc/HZ @ 60 KHz offset



1) I select the Voltage Control Ring Oscillator Type as my VCO structure.  I used the PSS analysis and PNOISE analysis.

Simulation condition

RC extraction net list

Spectre Model

Noise Mode=2

 

The simulation result is good enough to meet the specification.

Simulation result

Center Frequency: 10MHz

Phase Noise: -92dbc/HZ @60KHz offset



2) I taped out that VCO circuit and got the Sample. The measurement result is quite bad.

Measurement result

Center Frequency: 10MHz

Phase Noise: -80dbc/HZ @60KHz offset



So there is a big difference between the simulation result and measurement result. We had gotten a lot of help and support from  Cadence Singapore. but unfortunately, we haven't figure out what's the root cause.



What's my question is,

4) Is that SpectreRF PSS and PNOISE analysis suitable for the Ring Oscillator? Or PSS and PNOISE analysis is more suitable for LC type oscillator?

5) Is PNOISE result from the RC extraction net list more accurate?

6) Do we need extract the substrate (BULK) network in order to get more accurate result?

7) What's your suggestion on simulation methodology? Any special setting up is for Ring Oscillator phase noise simulation?

8) How to troubleshoot the big difference of PNOISE between the simulation result and measurement result? We assume the setting up of measurement is correct.


I appreciate all of you can help!
Thanks in advance!!

Raymond

Thanks! Paul,

Yes, you are right. The 60Khz is in the 1/f3 region.
And all other circuits were switched off when I did the measurement. So I suppose the substrate is quite.
But the VCO circuit itselt contents two basic blocks, one is the bias circuit, another is the  CCO(current control OSC).

I got the Spectre parameter from our customer. It seems they have all those 1/f parameter.


Below is my Spectre Model
.....
//$*mosfet bsim3v3 noimod=2 & 3 noise parameters:
+ noimod=2
+ noia=8.7526e+19
+ noib=79484
+ noic=-9.997e-13
+ ef=1.06
+ em=98174560
......

1) I was wondering the big difference between the simulation and measure result. So I add the RC extaction to my netlist to account the coupling effect between the noisy signal (CCO part) and quite signal(BIAS part). But the result from the RC extraction is still more or less same.

2) So I am wondering the power supply sharing between the BIAS circuit and CCO circuit will cause the big difference.

3) Even I am wondering the substrate coupling.

Since all those published papers never mentioned the the coupling effects, power supply noise and substrate noise when they describe the phase noise in oscillator. They only theoretically analyse phase noise coming from the device noise(1/f  noise, thermal noise and so on).

So I confuse that for a long while. Does that means the power supply noise, coupling noise and substrate noise are not important in analysis of the phase noise of OSC?

Do you have reference paper on that topic?Have you encounter same problem before? Any suggestions? Thanks for your help!

Raymond

Hi raymond,

  I came across the problem with my chip, see my post
http://www.designers-guide.com/Forum/?board=jitter;action=display;num=1064000788...

What process are you using? My chip was in 0.13u technology.  And also the noise model parameters
that you quoted are for NMOS or PMOS. I noticed that these parameters are quite high for NMOS compared to PMOS, meaning  NMOS has a lot more flicker noise than  PMOS.  Also, does your VCO run on regulated voltage? Is the regulator noise taken care of? What is the Kvco of your VCO? If this is high regulator noise can degrade the VCO phase noise considerably.

raymond wrote on Nov 10^th, 2003, 10:32pm:



REPECTED SIR,
    MYSELF DOING FINAL YEAR PROJECT ON RING VCO IN Mhz RANGE IN 0.18um CMOS Tech.. I DESIGNED THE SINGLE STAGE DELAY CELL USING PSPICE...  BUT I DON'T KNOW TO PROCEED THE NEXT STEP .... BY VIEWING DIFFERENT SITES I COME TO KNOW THAT BY INCREASING THE DELAY CELLS THE FREQUENCY WILL DECREASE .... CAN YOU SAY ME HOW TO EXECUTE THE SINGLE STAGE? HEREBY I ATTACHED BY PIC OF SINGLE STAGE DELAY CELL.. THANKS IN ADVANCE
BY REGARDS
RANI

You are missing a large number of things:

- What is the power supply over the ring oscillator and how is it held stable?
- What is the sensitivity of the ring oscillator to ground noise?
- How is the output of each stage buffered and distributed?
- What is the architecture of the ring oscillator?
- What is the model used for stage to stage cross coupling?
- What is number of delay cells used in the ring, and does the ring have the time to settle out before transitioning again?

There are many many things with ring oscillators to get them right, the theory of the loop is only the starting point.

Above is a brief list - then from there -

- What is the foundry used, what are the models for the transistors and and are those models valid?

I am guessing that you don't have real power sources (ideal voltage) contributing noise and ideal grounds as well. Also guessing that each delay cell in  the ring does not settle out before transitioning again, which leads to a lot more sensitivity to environment noise as well.

Most of the PLL papers published don't cover most of the important things needed to make a PLL ring oscillator run right.