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analog cmos design (Read 5514 times)
jitu
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analog cmos design
Nov 18th, 2003, 11:20pm
 
hi everybody...
           plz can someone help me out,or can guide me in the following problem i have encoutered while simulating the 900 Mhz LNA on spectreRf simulator.i have used bsim3 model,with the following circuit specfication-
Ls(inductor in the source branch)=2.5nH
Lg(inductor at  the  gate)=18.5nH
Ld(inductor at the drain)=15nH
bias current of 1.1mA and supply current voltage of 3.3V i have to achive a GAIN of 40db,but instead iam getting  attenuation at 900Mhz.
???plz anybody can tell me where i am going wrong.iam using 0.35um cmos process (TSMC) from mosis. ???
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naren
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Re: analog cmos design
Reply #1 - Nov 29th, 2003, 11:18pm
 
Hi
I am working on an LNA for 900MHz and I am using CSM 0.18u process.....I am also using SpectreRF for my simulation....I would like to ponder of a fewpoints

1) I think it is impossible to reach 40dB Shocked with the on-chip inductors of any process without increasing power dissipation to compensate losses in inductors particularly in the inductor at the drain of the cascode (Ld is it??)

2) Have you checked your bias points correctly?

3) How did you approach your design? did you take care of the series resistance of Lg and Ls when calculating gm of fet for acheiving matching?

4) and one more point is that your noise figure will surely shoot up and your design will oscillate surely....

I can give you more help if you can provide more information about the process itself....because I faced similar problems to you

bye
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jitendra
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Re: analog cmos design
Reply #2 - Nov 30th, 2003, 9:51am
 
hi naren,
             thax for ur suggestions.i was looking forward for someone's help.i hope that u will help me out.by the way the details which u wants me to tell u r as follows.
regarding my approach towards my design here by iam stating my approach..............
a)choosen  the value of Q = 3.
b)then the width of the transistor calculated by me using Leff = 0.30 um and Cox = 4.6fF/m^2 was 580 um.
c) choosing the value of Ls = 2 nH,wt calculated by me was 35.71 Grps.
d) then Lg =13 nH and Ld = 6nH for the capacitive load C= 2 pF
e) gm calculated by me  is 23.93 mS,also Veff = 0.057V with bias current of 1.5 mA.
these r few points which i have calculated while approching my design,regarding the series resistance of Lg nad Ls i have not taken them into consideration.by the what values should we use,
right now iam stuck up........... ??? ???
i will really be obliged to u if u can help me out, iam looking forward for ur help,hope that u will answer my quries.also plz do send ur email address where i can contact u.
bye.....
jitu.







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kokabanga
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Re: analog cmos design
Reply #3 - Dec 3rd, 2003, 9:08am
 
hi again....
I suggest that you check if your device is operating in the saturation region......check gate and source node voltages and find Vgs and see if it is roughly above the nominal vth.....the inductor Ls will surely have some series resistance with it which will surely drop some voltage and may make your mos be in cutoff ....just check vgs to be sure.....then check out the value of gm in cadence after doing a dc analysis also.....then if your gm is low....and I think your gm will be low....then increase your bias voltage at the gate and then check until your device has the gm you want....first do these things and then next plot the s11....your s11 will not be tuned to be minimum at 900MHz mostly then you will have to again add a external capacitor across the Gate and Source terminals and adjust its value until you get the minimum S11 point at 900MHz...even then you will not get very good matching...due to some series resistances of Ls and Lg.....I highly suggest you first check if your device is biased properly and then proceed onto the matching part....I will mail later when you have confirmed if your bias Id and associated gm have taken the proper values
good luck
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naren
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narendran
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Re: analog cmos design
Reply #4 - Jan 9th, 2004, 9:16am
 
hello jitu
what happened.......not heard from you?.....what happned?? were u able to bias precisely??....and obtain good input matching??.....what happened to the noise figure......btw how did u choose W of mosfet huh?....u must choose at the optimum value.....u must refer to thomas lee's paper for the method....hope u understand?....do mail me abt any problems...glad to help u out man...
regards
naren
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jeet
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Re: analog cmos design
Reply #5 - Mar 21st, 2004, 9:29pm
 
Hi Naren and jeetu,
I am designing an LNA facing the same problems as jeetu did. I have also read Naren's suggestion to jeetu and gonna follow them to see if my design works or not. If it doesn't i am gonna revert back to two of you and seek some help. Let me know if you two are still active on this forum or not? I will be highly obliged to hear from you.
Thanks
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kokabanga
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Re: analog cmos design
Reply #6 - May 20th, 2004, 3:40am
 
I am still here
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naren
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