Hi
I am working on an LNA for 900MHz and I am using CSM 0.18u process.....I am also using SpectreRF for my simulation....I would like to ponder of a fewpoints
1) I think it is impossible to reach 40dB
![Shocked Shocked](https://designers-guide.org/forum/Templates/Forum/default/shocked.gif)
with the on-chip inductors of any process without increasing power dissipation to compensate losses in inductors particularly in the inductor at the drain of the cascode (Ld is it??)
2) Have you checked your bias points correctly?
3) How did you approach your design? did you take care of the series resistance of Lg and Ls when calculating gm of fet for acheiving matching?
4) and one more point is that your noise figure will surely shoot up and your design will oscillate surely....
I can give you more help if you can provide more information about the process itself....because I faced similar problems to you
bye