I'm just a beginner, sorry for my poor question.
I donwloaded Ken's predicting PLL noise and Jitters PDF,but because of the language problem, i can not quite understand.I just want to know, how can I simulate the noise and jitter of a PLL(or a part of the PLL) just by clicking options and set some parameters, and start from the C@dence ADE? I am designing a anlog PLL, I have no idea about the verilog-A noise models can work with it. Who can tell me in detail but simplely what I should do step by step? Thanks a lot!