Well, your xtl node is supposed to be a floating node. However, if you connect the esd pmos transistor, there is a reverse biased diode from bulk to drain, which will charge the node to some voltage.  If you don't specify initial conditions for the voltage on xtl, the simulator assigns there some voltage. The higher this voltage the worse, because suppose the xtl voltage is @ 3.3 initially and the cap is charged to 3.3-1.25=2.05. When your input source goes to 2.75 the xtl voltage should go to 4.8v which will turn on the bulk-drain diode of the esd pmos transistor and you'll have big bulk current. Because your cap is big and your pulse time is small, you basically don't have enough time to discharge the cap and you see the voltage shifted up.
Run your simulation and check for bulk current. Also, put initial conditions for the xtl voltage, play with different values for it and see how this affects the behavior.
If this is to be a real circuit, you'll need something to fix the foltage of xtl.

If you use only a pmos esd transistor the xtl node gets charged to 3.3 through the drain-bulk diode (by the reverse current of it) - at least the simulator assumes so, since this diode is the only relatively conducting part connected to this node. Similar for the nmos esd only case, but there things happen towards ground. After all the simulation should start from some operating point.
Now, if this is a real circuit I just speculate that this is a crystal oscillator together with the inverter as an active element. If this is so, then there should be a resistor connected between the input and the output of the inverter for the purpose of setting the operating point and putting the inverter in its active region. In this case this resistor fixes the voltage of xtl and this node is not floating anymore. But this is only if my assumption about the real circuit is correct. If it is not, then I don't know.