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mas_serg

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Pass instance parameters
Mar 25^th, 2004, 6:26pm

Does anybody now how to pass Instance parameter to functional view during SpectreVerilog mixed mode simulation? For example invertor delay time for different types of a structure. It is not convenient to use different cells for different invertors. During analog simulation it is not problem: just add to symbol the CDS parameter "par_name" and write in pPar("par_name") in subcircuit component parameter field. But how to do it for mixed mode simulation? It creates analog and digital netlists separated and how to pass instance parameters to digital netlist I don't now.
Any ideas?

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jbdavid

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Re: Pass instance parameters
Reply #1 - Oct 2^nd, 2005, 6:36pm

Sorry, its quite easy to do in AMS but not in SpectreVerilog..
In AMSD you just declare the parameter in the model, and set on the instance..
I'm not sure Verilog-XL supports instance line parameter passing.. nor if the old netlister supports it..
AMS just costs 3 spectres while you run it..
or 1 spectre + 1 ncsim license.. (which is probably what your spectreVerilog is using anyway unless you haven't upgraded Verilog-XL yet.. )
jbd

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jbdavid
Mixed Signal Design Verification

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mas_serg

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Re: Pass instance parameters
Reply #2 - Oct 4^th, 2005, 4:23am

Thank you, jbd, for your reply.
I've already forgot about that my question. It was so long time ago.
I found solution about one year ago:
1. Add to the functional cellview line
parameter td=300; // default delay time
2.Add on an instance "User Property" with name "verilog" and type "hierProp", then -> expand and name "td", type "string" and unit 'timescale.
That is all.
May be it will be useful for somebody.

Thanks and best regarges,
Sam.

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rajdeep

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Re: Pass instance parameters
Reply #3 - Dec 24^th, 2007, 8:03am

Hi,

It's crazy to reply to a question which is 3yrs old!!
But I'm facing the problem now.
I'm using spectreVerilog simulator. I have been able to pass parameters to the functional/verilog
view from its instance using CDF parameters (not verilog->hierprop).

But how can I do it to another hierarchy down?? Say, I have a mixed signal module MIX. It consists of one verilogA module VA and another verilog module VER. I instantiate symbols of MIX at a schematic and want to pass parameters to the lower level modules i.e. VA an VER. It's easy to send it to the VA module, but the verilog netlister is not able to pass the parameter properly to the lower level module VA. It is picking up a garbage value.

Any help??
Rajdeep

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Design is fun, verification is a requirement.

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