Hi

I am having a bit of trouble calculating the jitter of a simple clock divider.  The clock divider is implemented in an Altera FPGA.  The output is monitored using an Agilent Spectrum Analyzer and phase noise plotted.  From there jitter is calculated by integrating.  I do believe the program I have written is correct, I have compared it to answers from examples given in papers about the topic.

Quoting your document  "Unlike in ripple counters, phase noise does not accumulate with each stage in synchronous counters"

I agree with the above but the test results tell me otherwise:

Output frequency        Jitter
100 Mhz                      12 ps
25  Mhz                       23 ps
6.25 Mhz                     98 ps

I would think the jitter would stay more or less the same as output frequency decreases.

Does any one have any ideas as to what is happening here ?  

Cheers

Dear justin

You can also use Communications system analyzer to directly measure jitters.