Ken had already write a set of clear papers to explain jitter/phasenoise in PLL. And he also introduce the way to simulate PLL jitters and phasenoise with vewrilog -A/AMS behavioral modeling.

However, when using cadence spectre to perform behvioral transient simulation, how fine should we set the accuracy settings? For example, since the behaviral models use Monte-Carlo like simulation, if uniform steps are applied, the maximum time step should be much smaller than the jitter to preserve the jitter behaviors. But this sytle would cost a lot of time.

I know ADS use sawtooth waveform to perform interpolation to optain timings accuracy finer than the minimum time steps in PLL simulations. This method is somewhat similar to switch from voltage domain to phase domain.

If I use verilog to model jitters, things seem to be easier since the simulation would be event-driven. Of course, I can switch the PLL modeling to the phase or frequency domain. But what I wonder is that-- how to preserve the accuracy of jitter simulation more efficiently? especially in low jitter systems.

By the way, I heard that Eldo can do transient simulation with noise. How can we modify the spectre simulation bench to perform such simulations, that is--to automatically generate noise voltage/current in devices in transient simulation.