jbdavid
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You can also use verilog-A there is an eye_diagram_generator in rfExamples - or rfLib.. this works on a timer.. but if your recieve clock is from a locked pll with some jitter model, you might want one that resets based on a trigger signal.
you might check bmslib (ships with IC5.033 and above) to if the clocked version made it in there..
this generates two signals.. a horizontal sweep and vertical signal and you use those to do plot the vertical vs the horizontal.. to see the eye diagram..
Of course if you are interested in ensuring a sufficient eye-opening, you might rather check that directly.. which requires a different verilog-A or AMS model.
Jbd
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