Hello everyone,

I am designing a VCO in a PLL which uses for clock generator in MCU. So its operating frequency is not very high, tuning range is about 10MHz~200MHz. And it will be implemented by CMOS 0.6um process with 5V power supply. In addition, the input control voltage also needs wide control range.

In many specs, I focus on the lower phase noise characteristics and higher PSRR. Firstly, due to the low frequency application, I select the Ring VCO. However, there are so lots of IEEE papers about the Ring VCO that I can't decide which one is best for me.

So please suggest me the achitecture of Ring VCO! I would like use the differential cascode structure to build my Ring VCO, how do you think about its performence?
Thanks in advance!

Best Regards,
Vincent