Hi Ken,
I am working with some design using Verilog-A,
in which the goal of the design is "to read an external disk data into a local module of a top-level schematic".
The data is basically a collection of pure numbers that are generated by other products such as MATLAB or C, and it will be used as sort of gain or weighting factor in a local module. In that sense, it has neither
"voltage" or "current" dimension but just pure numbers.
I want to read them at regular clock times set by a local module using "timer event" statement of Verilog-A.
I tried "vsource" mapping using the option of "pwl" or "pulse" type but they don't work successfully because
I couldn't determine the time format that is required
by "vsource". In my case the data really don't need to have time-dependency.
I tried to do this in many ways and talked to CADENCE feedback a lot so far but they didn't give me a clear
solution. In my opinion, reading data from disk file
is one of common operations that a variety of language
program today can offer.
In addition, I wonder why there is no read statements
in Verilog-A langhuage. You see there are a couple of
"write statements" for example, $fdisplay, $fstrobe,
and $fwrite.
It would be much appreciated if you can help me with soulutions for this problem.
Best regards.
Donghyun Kim
Analog ASICS Lab.
amsung Electromechanics Co.
Tel: +82-31-210-6412
Fax: +82-31-210-6380