I assume that by macro model you mean a behavioral model composed of simulator primitives like resistors, capacitors, controlled sources, etc. as opposed to a behavioral model written in VerilogA or some other modeling language.

I might use a macro model if I wanted to simulate specific nonlinearities of an active filter, especially if the filter had lots of feedback loops. It is often easier to duplicate the circuit structure with ideal primitives than to extract the modeling equations. The structural nature of a macro model makes it easier to surgically remove various impairments to diagnose a particular symptom.

I would use a language based model for a phaselock loop or switch-mode power supply. I spent a great deal of time building macro models of power systems and it was more art and luck than science.

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The modeling method I did not mention is device-level modeling. Device-level models simulate the circuit component-for-component, i.e. as close to the true schematic as possible, including parasitic elements. For example, if you want to simulate the reverse recovery of a diode so you can design a snubber circuit, you will want to use detailed device models, not macro models. Marco models usually do not include things like reverse recover of diodes and nonlinear parasitic elements.

If you want to simulate control loop dynamics, dynamics covering thousands of switching cycles, you may want to use behavioral models. There are two kinds of behavioral models, brute force and state space averaged. I usually used the brute force models only to validate the much faster state space averaged models. It probably makes sense to use a marco model for the brute force model. The marcro model would use ideal switches and dioces and drive them with ideal controlled sources. However, I think the state space averaged models are best modeled with a modeling language.

Macro models become cumbersome when the circuit's behavior changes character. For example, consider a buck DC/DC converter. The buck converter has two conduction modes, one where the inductor current never goes to zero and one where the inductor current is zero for a finite duration of each switching cycle. In the discontinuous conduction mode, the inductor stops being a state variable; it no longer stores energy from cycle to cycle. The inductor is replaced by an algebraic constraint relating voltages and currents. At the time I worked on this problem, SPICE had no behavioral language (like VerilogA or even single-line behavioral sources). I had to resort to ideal diodes and controlled sources to switch between modes. My macromodels worked, but not after I nursed the models into convergence by relaxing numerical options and inserting zero-voltage sources to manipulate the netlisting order. I modeled power electronics for perhaps 14 years but have not been involved in power electronics for about 8 years now. However, if I had to return to it I would definitely use VerilogA and/or VerilogAMS or some other behavioral language.

In the mid 80s to early 90s, you could always find a paper or two every year on some new macro model. I have not looked too hard but I suspect there aren't as many papers on behavioral models of DC/DC converters any more because behavioral modeling languages remove most of the problems. It is a lot easier to code up multi-mode behavior using "if" statements and "@cross" statements than to synthesize a fictitious circuit composed of ideal diodes and controlled sources to switch modes.

If you are interested in macro models, I would try to find the references listed below.  However, with VerilogA on the scene I wonder they are still in print.

Steven M. Sandler, "SMPS Simulation with SPICE3". McGraw Hill. 1997. ISBN 0-07-913227-8.

Daniel M. Mitchell, "DC-DC Switching Regulator Analysis". McGraw-Hill. 1988. ISBN 0-07-042597-3

Yim-Shu Lee, "Computed-Aided Analysis and Design of Swtich-Mode Power Supplies". Dekker. 1993. ISBN 0-8247-8803-6