In some cases adding power supply may help.

Besides, if you are developing VHDL-AMS models, it is highly desirable to add models of SMPS power supplies - step up (boost) and step down (buck).

Alex

Paul,

  There are a lot of different philosophies on this topic and the answer depends what you are trying to do.  If you are just building a simple model to test an idea than you probably don't need power supply connections. However, if you plan to anything close to design, then you will need to add power supply pins. In fact, I would all the pins at all the levels.  "Pin correct" behavior modeling is important for a couple of reasons. First, is is useful if you share models with other designers, in particular, system designers. System designers need to interface to the block so having all the pins and modeling them correctly are important. For example, is signal X active hi/active lo, is the output 2s complement/straight binary, ...  Next, it will help you out during design for the same reason, that is, it will allow you verify all the modes of operation for a design. On some recent models, we included effects such as lock-out, if the power supply drops below a certain voltage the block stops working allowing us to model start-up.  In addition, pin-correct models allow you to debug your testbenches and verification strategy before starting transistor level design. Debuggin at the transistor level is a pain, nobody wants to wait 5 hours for a simulation to complete only to find a testbench issue. Finally, pin correct means all the symobls and the design heirarchy are correct which again makes transistor level design al lot easier.

   So if you are designing a channel filter for a Wireless application:
Case I: what is the effect of open loop gain on the transfer function? don't need power pins
Case II: Does the filter calibration algorithm work correctly?  probably need power supply pins, that is, does the filter start-up, does the calibration block start-up, is calibration disabled when complete, ...

   Sorry for the long answer, hope it helps, or at least stimulates some more discussion.

                                                     Best Regards,

                                                        Sheldon

However, this discussion is  posted in the "VHDL-AMS" area. If I were doing a mixed signal system level simulation, I would want to include power supply pins and definitely simulate power up. In real life, digital blocks don't work without a power supply and I don't think it's safe to assume the supply will always be properly connected or at the proper level. I would take advantage of the "AMS" part of the language to ensure the digital supplies are at least present and have the proper polarity.

As for the auxiliary question, if either method is implemented properly, I don't see how the rest of the system can tell the difference. I suppose I would use the two single ended sources because that approach has one less node.

Paul,

The dependence of digital blocks on analog signals is, in my opinion, the main reason for investing in a mixed signal tool. If we can't find a way to use the language for something as simple as a test for proper power supply voltage within an otherwise digital block, then I see no reason to invest in mixed signal simulators at all. At this point I must confess that my group is still trying to justify an investment in mixed signal tools. I am therefore very interested in why you don't think the AMS part of VHDL-AMS is the answer to your problem.

Eugene, Art,

thanks for your comments. I fully agree that the optimum solution depends on the type of simulations to be done. I will focus here on system-level (mixed analog-digital) verification and try to answer Eugene's question in this context. In my former job, we tended to implement start-up behavior of analog parts as a function of supply voltage. When combining the VHDL-AMS models of these parts with the digital parts in VHDL (could also be Verilog), the following problems arose:
a) outputs of analog part depend on power supply, but outputs of digital part do not depend on power supply
b) using VHDL on top (seems to be faster in simulation), supplies are not present in the top-level simulation netlist

Discussion of a)
to make the digital part supply sensitive, we would have to replace the digital blocks by a VHDL-AMS description, which could be done using an alternate power sensitive cell library, but would tremendously slow down simulation. An alternative could be inserting some supply sensitive buffers in between digital and analog parts, for simulation only. What's your point of view?

Discussion of b)
As the digital design flow (from simulation to synthesis and P&R) makes abstraction of supplies, these are defined in a separate file for the P&R tools and not directly available to the simulator. If you operate one of the changes discussed before, then supplies can be added to the top-level netlist, but this netlist is different from the one used for P&R. So you can validate the system, but it will not guarantee that the supplies are routed correctly in full-chip verification. But post-layout verification is probably not your concern, Eugene, is it? For this, I guess you have to rely on table-based transistor-level simulators like MachTA (Mentor). Cadence certainly has an equivalent simulator, but I don't know its name. Somebody certainly can give a hint on this.

Paul

Right Eugene,

I agree that we must find ways to make designers of different parts talk to each other. My only concern in this approach is that stimulating the discussion about supply voltages and interfaces this late in the flow may be costly. It would be preferrable to introduce this kind of modeling early in the flow to avoid redesigning part because of this kind of issue. But I agree that this kind of model should definitely be somewhere in the flow.

Regarding post-layout verification, I possibly misused the term "post-layout". The topic I wanted to address is about full-chip interconnect verification. I do not mean timing closure or corner simulation, just verifying that the chip assembly has been done correctly. Assembling digital and analog parts with sometimes several hundred signals running in between means that the system designer can easily mix two of them during the assembly process. Running a simulation using the top-level (typically Verilog-) netlist seems to be a must to me. And using a wrapper around the digital parts means parsing and modifying the netlist, thus reducing the verification coverage. Mixed-signal simulation would be the fastest simulation, but in order to consider supply connections, a fast transistor-level simulation may be an option, as already mentioned. What do you think? Maybe you have a different way to perform this kind of verification?

Paul

Eugene,

Maybe some people with more knowledge on the latest developments in the tools will join this discussion to share their opinion. I heard about the improvements of the latest Cadence tools using OpenAccess Database, but I am not sure that the present problem has a solution using these tools. I am not saying that mixed-signal (MS) simulation is not helpful in system-level functional verification, but I think some parts are still missing in the flow to achieve this. Notice that even for purely digital chips, some people use fast transistor-level (table-based) simulators to perform functional verification and power estimation. Maybe this will be the way to go, these simulators are indeed quite fast, but I had some trouble running switched-cap parts in the system (maybe that's solved now, I did not try with the latest tools).

I will try to go through the flow to explain why I consider MS simulations as not ready for post-assembly full-chip verification.
Digital blocks:
- simulation in Verilog/VHDL (no supplies considered)
- synthesis (no supplies considered)
- P&R (supplies defined in separate file)
Analog blocks:
- transistor-level simulation
- custom layout
Assembly (that's where the problems appear) can either be done with a digital tool" (e.g. Cadence SE) or a "MS tool" (e.g. Cadence ICC). Both use abstracts for the blocks. The first has a definition of supplies in a separate file and gets routing info in a Verilog file (without supplies). In this "Verilog-on-top" simulation, it is definitely is hard to include supplies. The second gets a schematic (or equivalent netlist), resulting in a "spice-on-top" type simulation, which of course contains supplies. The problem is that these supplies will be used in the analog blocks, but the digital part will not consider them. As already mentioned in an earlier post, I see two options: using wrappers to make the interface of the digital blocks supply sensitive, or use a supply sensitive cell library, which then still needs a netlist with supplies of the digital part. Both options require modifications of the netlist, and these must be done in a well-controlled manner not to reduce verification coverage.

To your questions:
1) In my opinion, an automated solution to this would be the least error prone.
2) The "translation" should not be too long, but if you need to simulate a big digital block in V*-AMS, it becomes a really long simulation.
3) AFAIK, the current chip assembly tools do not operate with MS languages, and BTW, this is not the real problem. The translation of the digital part to an MS language is the problem, and I am sure the digital flow (synthesis, P&R) do not operate with MS languages.

It seems to me there is no off-the-shelf solution to this, but don't hesitate to correct me if I am wrong.

Paul