ywguo
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Hi, Sunny,
If you need design PECL/ECL output driver, I would like to list all the relevant papers and application notes I had read when I studied PECL several years ago. At that time, I was a graduate student. :)
[4] Andrea Boni, “1.2-Gb/s True PECL 100K Compatible I/O Interface in 0.35-mm CMOS,” IEEE Journal of Solid State Circuits, vol. 36, pp. 979-987, Jun. 2001.
[5] Hormoz Djahanshahi, Flemming Hansen, and C. André T. Salama, “Gigabit-per-Second, ECL-Compatible I/O Interface in 0.35-mm CMOS,” IEEE Journal of Solid State Circuits, vol. 34, pp. 1074-1083, Aug. 1999.
[7] “S2046/2047 Gigabit Ethernet Chipset Device Specification,” Applied Micro Circuits Corporation, San Diego, CA, 2000.
[8] F. Alicke, F. Bartholdy, S. Blozis, F. Dehmelt, P. Forstner, N. Holland, J. Huchzermeier, “Comparing Bus Solutions,” Texas Instruments, Application Report, SLLA067, Mar. 2000.
[10] K. Lee, S. Kim, Y. Shin, D-K. Jeong, G. Kim, V. DaCosta, D. Lee, “A Jitter-Tolerant 4.5Gb/s CMOS Interconnect for Digital Display”, ISSCC Digest of Technical Papers, Feb. 1998, pp.302-303.
[11] Richard Gu, James M. Tran, Heng-Chih Lin, Ah-Lyan Yee, Martin Izzard, “A 0.5 -3.5Gb/s Low-Power Low-Jitter Serial Data CMOS Transciever”, ISSCC Digest of Technical Papers, Feb. 1999, pp.352-353.
[12] Michel S. J. Steyaert, Wout Bijker, Pieter Vorenkamp, and Jan Sevenhans, “ECL-CMOS and CMOS-ECL Interface in 1.2-mm CMOS for 150-MHz Digital ECL Data Transmission Systems,” IEEE Journal of Solid State Circuits, vol. 26, pp.18-24, Jan. 1999.
[14] “F100K ECL 300 Series Datasheet,” National Semiconductor Corp., Santa Clara, CA, Sep. 1998.
[15] Kal Mustafa, “Interfacing Between LVPECL, LVDS and CML,” Texas Instruments, Application Report, SCAA045, Dec. 20001.
I hope they are helpful.
Best regards,
Yawei
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