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Sunny

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IO for accurate PLL measurement
Jul 20^th, 2004, 6:09pm

Hi,

I'm designing a 50 ohm off-chip driver for a PLL (100Mhz to 1Ghz output).

1. How important is it to use differential IO in order to measure phase noise/jitter performance?

2. I have tried using a huge inverter with a parasitic model of the pad/package (pi network) 1pF@pad, 5nH @ bond-wire, and
10pF @ pin followed by 50 ohm termination. The signal at the pad looks wierd due to ringing in the parasitic network, even
though the output turns out more sinusoidal (filtered).

I am concerned that this approach, being single-ended would be vulnerable to noise coupling/noise in ground loop etc. and
would give inaccurate jitter measurements.

3. The other option which I've read about is using ECL/PECL drivers, which I'm not sure how to use, since I don't have
bipolars to work with, and using a stand-alone ECL driver IC would require driving the CMOS signals off-chip first anyway!
I'm not aware of a way to get the low output impedance equivalent to that at the emitter of a bipolar device, and I'm
not even sure this is necessary. ???

Thanks
sunny3funny@yahoo.com

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Paul

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Posts: 351
Switzerland

Re: IO for accurate PLL measurement
Reply #1 - Jul 22^nd, 2004, 7:58am

Hi Sunny,

If you have a differential PLL, I would go for a differential output driver. You will have symmetric load, which is probably important for your PLL. Regarding PN/jitter, the noise of your driver will of course add to the PLL noise. Going from differential PLL to a single-ended driver will probably change your rise/fall times and affect you jitter measurement.

In CMOS, you can design equivalent ECL gates using MOS devices, which is currently called current-mode logic (there are a couple of other names used). Have a look at the following paper (10Gb/s output):

OC-192 transmitter and receiver in standard 0.18-um CMOS
Cao, J., Green, M. et al.
IEEE Journal of Solid-State Circuits, Dec. 2002

As you operate at lower frequencies, you won't need the on-chip inductors. Just notice that this output is typically 400mVpp differential, so check your measurement equipment if you can use this.

Paul

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ywguo

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Posts: 943
Shanghai, PRC

Re: IO for accurate PLL measurement
Reply #2 - Jul 24^th, 2004, 1:32am

Hi, Sunny,

If you need design PECL/ECL output driver, I would like to list all the relevant papers and application notes I had read when I studied PECL several years ago. At that time, I was a graduate student. :)

[4] Andrea Boni, “1.2-Gb/s True PECL 100K Compatible I/O Interface in 0.35-mm CMOS,” IEEE Journal of Solid State Circuits, vol. 36, pp. 979-987, Jun. 2001.

[5] Hormoz Djahanshahi, Flemming Hansen, and C. Andr� T. Salama, “Gigabit-per-Second, ECL-Compatible I/O Interface in 0.35-mm CMOS,” IEEE Journal of Solid State Circuits, vol. 34, pp. 1074-1083, Aug. 1999.

[7] “S2046/2047 Gigabit Ethernet Chipset Device Specification,” Applied Micro Circuits Corporation, San Diego, CA, 2000.

[8] F. Alicke, F. Bartholdy, S. Blozis, F. Dehmelt, P. Forstner, N. Holland, J. Huchzermeier, “Comparing Bus Solutions,” Texas Instruments, Application Report, SLLA067, Mar. 2000.

[10] K. Lee, S. Kim, Y. Shin, D-K. Jeong, G. Kim, V. DaCosta, D. Lee, “A Jitter-Tolerant 4.5Gb/s CMOS Interconnect for Digital Display”, ISSCC Digest of Technical Papers, Feb. 1998, pp.302-303.

[11] Richard Gu, James M. Tran, Heng-Chih Lin, Ah-Lyan Yee, Martin Izzard, “A 0.5 -3.5Gb/s Low-Power Low-Jitter Serial Data CMOS Transciever”, ISSCC Digest of Technical Papers, Feb. 1999, pp.352-353.

[12] Michel S. J. Steyaert, Wout Bijker, Pieter Vorenkamp, and Jan Sevenhans, “ECL-CMOS and CMOS-ECL Interface in 1.2-mm CMOS for 150-MHz Digital ECL Data Transmission Systems,” IEEE Journal of Solid State Circuits, vol. 26, pp.18-24, Jan. 1999.

[14] “F100K ECL 300 Series Datasheet,” National Semiconductor Corp., Santa Clara, CA, Sep. 1998.

[15] Kal Mustafa, “Interfacing Between LVPECL, LVDS and CML,” Texas Instruments, Application Report, SCAA045, Dec. 20001.

I hope they are helpful.

Best regards,

Yawei

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Sunny

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Posts: 4

Re: IO for accurate PLL measurement
Reply #3 - Jul 29^th, 2004, 1:19pm

Hi,

Thanks, Paul and Yawei for your responses.

Paul, the OC-192 paper's driver uses a BGA package, and hence has low bondwire inductances.
I'm working with TQFP. Perhaps this is why I see ringing for some values.
What bothers me is that for some values of parasitic L,C, the ringing takes place even as
the waveform transitions.
This might cause inaccurate jitter measurements! Is there a simple solution to this.
I have seen one which uses a pulsed bias topology (ref. 5 in Yawei's list of papers), but looks quite complicated, and would
be a project in itself.
Pl. let me know if you have any suggestions.

Thanks

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